{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:36:12Z","timestamp":1750221372127,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,11,12]],"date-time":"2017-11-12T00:00:00Z","timestamp":1510444800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,11,12]]},"DOI":"10.1145\/3148173.3148190","type":"proceedings-article","created":{"date-parts":[[2017,10,31]],"date-time":"2017-10-31T12:31:37Z","timestamp":1509453097000},"page":"1-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Applying Temporal Blocking with a Directive-based Approach"],"prefix":"10.1145","author":[{"given":"Shota","family":"Kuroda","sequence":"first","affiliation":[{"name":"Tokyo Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshio","family":"Endo","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Matsuoka","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,11,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113449"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470813"},{"volume-title":"IEEE\/ACM SC'10","author":"Nguyen A.","key":"e_1_3_2_1_3_1","unstructured":"A. Nguyen , N. Satish , J. Chhugani , C. Kim , and P. Dubey : 3.5-D blocking optimization for stencil computations on modern CPUs and GPUs . IEEE\/ACM SC'10 , 13 pages (2010). A. Nguyen, N. Satish, J. Chhugani, C. Kim, and P. Dubey: 3.5-D blocking optimization for stencil computations on modern CPUs and GPUs. IEEE\/ACM SC'10, 13 pages (2010)."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1137\/140991133"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICMMT.2010.5524901"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTER.2013.6702633"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2016.0137"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989493.1989508"},{"volume-title":"IEEE\/ACM SC'11","author":"Maruyama N.","key":"e_1_3_2_1_9_1","unstructured":"N. Maruyama , T. Nomura , K. Sato , S. Matsuoka : Physis: an implicitly parallel programming model for stencil computations on large-scale GPU-accelerated supercomputers , IEEE\/ACM SC'11 , 12pages (2011). N. Maruyama, T. Nomura, K. Sato, S. Matsuoka: Physis: an implicitly parallel programming model for stencil computations on large-scale GPU-accelerated supercomputers, IEEE\/ACM SC'11, 12pages (2011)."},{"volume-title":"IEEE\/ACM SC'16","author":"Muranushi T.","key":"e_1_3_2_1_10_1","unstructured":"T. Muranushi , H. Hotta , J. Makino , S. Nishizawa , H. Tomita , K. Nitadori , M. Iwasawa , N. Hosono , Y. Maruyama , H. Inoue , H. Yashiro , Y. Nakamura : Simulations of Below-Ground Dynamics of Fungi: 1.184 Pflops Attained by Automated Generation and Autotuning of Temporal Blocking Codes , IEEE\/ACM SC'16 , 11pages (2016). T. Muranushi, H. Hotta, J. Makino, S. Nishizawa, H. Tomita, K. Nitadori, M. Iwasawa, N. Hosono, Y. Maruyama, H. Inoue, H. Yashiro, Y. Nakamura: Simulations of Below-Ground Dynamics of Fungi: 1.184 Pflops Attained by Automated Generation and Autotuning of Temporal Blocking Codes, IEEE\/ACM SC'16, 11pages (2016)."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1375581.1375595"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626412500107"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"e_1_3_2_1_14_1","volume-title":"The BSD Conference","author":"Lattner C.","year":"2008","unstructured":"C. Lattner : LLVM and Clang: Next generation compiler technology , The BSD Conference ( 2008 ). C. Lattner: LLVM and Clang: Next generation compiler technology, The BSD Conference (2008)."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15582-6_49"}],"event":{"name":"SC '17: The International Conference for High Performance Computing, Networking, Storage and Analysis","sponsor":["SIGHPC ACM Special Interest Group on High Performance Computing, Special Interest Group on High Performance Computing","IEEE CS"],"location":"Denver CO USA","acronym":"SC '17"},"container-title":["Proceedings of the Fourth Workshop on the LLVM Compiler Infrastructure in HPC"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3148173.3148190","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3148173.3148190","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:34Z","timestamp":1750213594000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3148173.3148190"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11,12]]},"references-count":15,"alternative-id":["10.1145\/3148173.3148190","10.1145\/3148173"],"URL":"https:\/\/doi.org\/10.1145\/3148173.3148190","relation":{},"subject":[],"published":{"date-parts":[[2017,11,12]]},"assertion":[{"value":"2017-11-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}