{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:26:52Z","timestamp":1763724412568,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2018,6,11]],"date-time":"2018-06-11T00:00:00Z","timestamp":1528675200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2018,7,31]]},"abstract":"<jats:p>As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this article, we present compact and accurate timing macro modeling, which is the key to efficient and accurate hierarchical timing analysis. Our goal is to contain only a minimal amount of interface logic in our timing macro model. The main idea is to separate the interface logic into variant and constant timing regions. Then, the variant timing region is reserved for accuracy, while the constant timing region is reduced for compactness. For reducing the constant timing region, we propose anchor pin insertion and deletion by generalizing existing timing graph reduction techniques. Furthermore, we devise a lookup table index selection technique to achieve high model accuracy over the possible operating condition range. Compared with two common models used in industry, extracted timing model and interface logic model, our model has high model accuracy and small model size. Based on the TAU 2016 and 2017 timing macro modeling contest benchmark suites, our results show that our algorithm delivers superior efficiency and accuracy: Hierarchical timing analysis using our model can significantly reduce runtime and memory compared with flat timing analysis on the original design. Moreover, our algorithm outperforms TAU 2016 and 2017 contest winners in model accuracy, model size, model generation performance, and model usage performance.<\/jats:p>","DOI":"10.1145\/3149818","type":"journal-article","created":{"date-parts":[[2018,6,12]],"date-time":"2018-06-12T12:15:55Z","timestamp":1528805755000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["iTimerM"],"prefix":"10.1145","volume":"23","author":[{"given":"Pei-Yu","family":"Lee","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Iris Hui-Ru","family":"Jiang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Roosevelt Road, Taipei, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2018,6,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451964"},{"key":"e_1_2_1_2_1","unstructured":"Babul Anunay. 2013. Hierarchical Timing Concepts. EDN Network. Retrieved from http:\/\/www.edn.com\/design\/integrated-circuit-design\/4423327\/Hierarchical-timing-concepts.  Babul Anunay. 2013. Hierarchical Timing Concepts. EDN Network. Retrieved from http:\/\/www.edn.com\/design\/integrated-circuit-design\/4423327\/Hierarchical-timing-concepts."},{"key":"e_1_2_1_3_1","unstructured":"Sunil Walia. 2011. Reducing turnaround time with hierarchical timing analysis. EE Times. Retrieved from http:\/\/www.eetimes.com\/document.asp?doc_id=1279120.  Sunil Walia. 2011. Reducing turnaround time with hierarchical timing analysis. EE Times. Retrieved from http:\/\/www.eetimes.com\/document.asp?doc_id=1279120."},{"volume-title":"Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU\u201913)","year":"2013","author":"Visweswariah Chandu","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513956"},{"key":"e_1_2_1_6_1","unstructured":"Liberty user guides and reference manual suite version 2013.03. 2013. Retrieved from https:\/\/www.synopsys.com.  Liberty user guides and reference manual suite version 2013.03. 2013. Retrieved from https:\/\/www.synopsys.com."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513957"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233584"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/2691365.2691488"},{"volume-title":"TAU 2016 Timing contest on macro modeling. In Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'16)","year":"2016","author":"Hu Jin","key":"e_1_2_1_10_1"},{"volume-title":"TAU 2017 Timing contest on macro modeling. In Proceedings of the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'17)","year":"2017","author":"Chen Song","key":"e_1_2_1_11_1"},{"key":"e_1_2_1_12_1","unstructured":"J. Bhasker and Rakesh Chadha. 2009. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer.   J. Bhasker and Rakesh Chadha. 2009. Static Timing Analysis for Nanometer Designs: A Practical Approach. Springer."},{"volume-title":"Proceedings of the 2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'14)","author":"Huang Tsung-Wei","key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825861"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840943"},{"volume-title":"Proceedings of IEEE\/ACM International Conference on Computer-Aided Design (ICCAD'15)","author":"Huang Tsung-Wei","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3036674"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3149818","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3149818","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:18Z","timestamp":1750213578000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3149818"}},"subtitle":["A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis"],"short-title":[],"issued":{"date-parts":[[2018,6,11]]},"references-count":17,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2018,7,31]]}},"alternative-id":["10.1145\/3149818"],"URL":"https:\/\/doi.org\/10.1145\/3149818","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2018,6,11]]},"assertion":[{"value":"2017-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-06-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}