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Syst."],"published-print":{"date-parts":[[2018,3,31]]},"abstract":"<jats:p>\n            While plentiful on-chip memory is necessary for many designs to fully utilize an FPGA\u2019s computational capacity, SRAM scaling is becoming more difficult because of increasing device variation. An alternative is to build FPGA block RAM (BRAM) from magnetic tunnel junctions (MTJ), as this emerging embedded memory has a small cell size, low energy usage, and good scalability. We conduct a detailed comparison study of SRAM and MTJ BRAMs that includes cell designs that are robust with device variation, transistor-level design and optimization of all the required BRAM-specific circuits, and variation-aware simulation at the 22nm node. At a 256Kb block size, MTJ-BRAM is 3.06\u00d7 denser and 55% more energy efficient and its\n            <jats:italic>F<\/jats:italic>\n            <jats:sub>\n              <jats:italic>max<\/jats:italic>\n            <\/jats:sub>\n            is 274MHz, which is adequate for most FPGA system clock domains. We also detail further enhancements that allow these 256 Kb MTJ BRAMs to operate at a higher speed of 353MHz for the streaming FIFOs, which are very common in FPGA designs and describe how the non-volatility of MTJ BRAM enables novel on-chip configuration and power-down modes. For a RAM architecture similar to the latest commercial FPGAs, MTJ-BRAMs could expand FPGA memory capacity by 2.95\u00d7 with no die size increase.\n          <\/jats:p>","DOI":"10.1145\/3154425","type":"journal-article","created":{"date-parts":[[2018,1,29]],"date-time":"2018-01-29T13:48:05Z","timestamp":1517233685000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs"],"prefix":"10.1145","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0511-443X","authenticated-orcid":false,"given":"Kosuke","family":"Tatsumura","sequence":"first","affiliation":[{"name":"Toshiba Corporation, Kawasaki, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sadegh","family":"Yazdanshenas","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,1,26]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.131"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe (DATE\u201913)","author":"Bi X."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847281"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology (FPT\u201912)","author":"Bsoul A."},{"key":"e_1_2_1_6_1","volume-title":"Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. 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