{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:47Z","timestamp":1750221287504,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2018,1,31]],"date-time":"2018-01-31T00:00:00Z","timestamp":1517356800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China NSFC","doi-asserted-by":"crossref","award":["91538202 and 91338103"],"award-info":[{"award-number":["91538202 and 91338103"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"new strategic industries development projects of Shenzhen City","award":["JCYJ20160520140157342 and CXZZ20150928165834560"],"award-info":[{"award-number":["JCYJ20160520140157342 and CXZZ20150928165834560"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2018,1,31]]},"abstract":"<jats:p>\n            Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair \u201cremedies\u201d cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC\/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write\/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC\u2019s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes\u2014(585,512) and (683,512)\u2014augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10\n            <jats:sup>2<\/jats:sup>\n            (10\n            <jats:sup>4<\/jats:sup>\n            ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.\n          <\/jats:p>","DOI":"10.1145\/3154836","type":"journal-article","created":{"date-parts":[[2018,3,9]],"date-time":"2018-03-09T13:27:48Z","timestamp":1520602068000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM"],"prefix":"10.1145","volume":"14","author":[{"given":"Bohua","family":"Li","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yukui","family":"Pei","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wujie","family":"Wen","sequence":"additional","affiliation":[{"name":"Florida International University, Miami, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,3,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429401"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCNC.2013.6504145"},{"key":"e_1_2_1_3_1","unstructured":"CCSDS. 2007. Low Density Parity Check Codes for Use in Near-Earth and Deep Space Applications. Orange Book Experimental Specification. Consultative Committee for Space Data Systems (CCSDS).  CCSDS. 2007. Low Density Parity Check Codes for Use in Near-Earth and Deep Space Applications. Orange Book Experimental Specification. Consultative Committee for Space Data Systems (CCSDS)."},{"key":"e_1_2_1_4_1","unstructured":"Zhiqiang Cui Zhongfeng Wang and Xinmiao Zhang. 2012. Reduced-complexity column-layered decoding and implementation for LDPC codes. arXiv:1204.2577 (2012).  Zhiqiang Cui Zhongfeng Wang and Xinmiao Zhang. 2012. Reduced-complexity column-layered decoding and implementation for LDPC codes. arXiv:1204.2577 (2012)."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201905)","author":"Hosomi M.","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"volume-title":"Proceedings of the 2010 Symposium on VLSI Technology.","author":"Ishigaki T.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7427985"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2374291"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2013.07.036"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTCFall.2016.7880909"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.9"},{"key":"e_1_2_1_15_1","unstructured":"Shu Lin and D. J. Costello. 2004. Error Control Coding. Pearson Education India.  Shu Lin and D. J. Costello. 2004. Error Control Coding. Pearson Education India."},{"key":"e_1_2_1_16_1","doi-asserted-by":"crossref","unstructured":"Jianhua Lu Xiaoming Tao and Ning Ge. 2015. An LDPC code design with sub-matrix structure. In Structural Processing for Wireless Communications. 45--54.  Jianhua Lu Xiaoming Tao and Ning Ge. 2015. An LDPC code design with sub-matrix structure. In Structural Processing for Wireless Communications. 45--54.","DOI":"10.1007\/978-3-319-15711-5_4"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/APCC.2013.6765990"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/18.748992"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/18.748992"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:19961141"},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication","volume":"1","author":"Pei Yukui","year":"2004"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/18.910577"},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA\u201911)","author":"Smullen Clinton W.","key":"e_1_2_1_23_1"},{"key":"e_1_2_1_24_1","unstructured":"Storage Industry Summit. 2016. Retrieved from http:\/\/www.snia.org\/sites\/default\/files\/NVM\/2016\/presentations\/ Panel_1_Combined_NVM_Futures%20Revision.pdf.  Storage Industry Summit. 2016. Retrieved from http:\/\/www.snia.org\/sites\/default\/files\/NVM\/2016\/presentations\/ Panel_1_Combined_NVM_Futures%20Revision.pdf."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/2971808.2972108"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/2561828.2561830"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228580"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593220"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629936"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2004.823508"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.5555\/2132325.2132435"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2012.2203589"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429498"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.3390\/ma9010041"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3154836","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3154836","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:27Z","timestamp":1750212687000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3154836"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1,31]]},"references-count":36,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2018,1,31]]}},"alternative-id":["10.1145\/3154836"],"URL":"https:\/\/doi.org\/10.1145\/3154836","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2018,1,31]]},"assertion":[{"value":"2017-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-03-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}