{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T03:10:05Z","timestamp":1775790605218,"version":"3.50.1"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"POPL","license":[{"start":{"date-parts":[[2017,12,27]],"date-time":"2017-12-27T00:00:00Z","timestamp":1514332800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Program. Lang."],"published-print":{"date-parts":[[2018,1]]},"abstract":"<jats:p>The integration of transactions into hardware relaxed memory architectures is a topic of current research both in industry and academia. In this paper, we provide a general architectural framework for the introduction of transactions into models of relaxed memory in hardware, including the SC, TSO, ARMv8 and PPC models. Our framework incorporates flexible and expressive forms of transaction aborts and execution that have hitherto been in the realm of software transactional memory. In contrast to software transactional memory, we account for the characteristics of relaxed memory as a restricted form of distributed system, without a notion of global time. We prove abstraction theorems to demonstrate that the programmer API matches the intuitions and expectations about transactions.<\/jats:p>","DOI":"10.1145\/3158106","type":"journal-article","created":{"date-parts":[[2017,12,29]],"date-time":"2017-12-29T14:21:49Z","timestamp":1514557309000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Transactions in relaxed memory architectures"],"prefix":"10.1145","volume":"2","author":[{"given":"Brijesh","family":"Dongol","sequence":"first","affiliation":[{"name":"Brunel University London, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Radha","family":"Jagadeesan","sequence":"additional","affiliation":[{"name":"DePaul University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Riely","sequence":"additional","affiliation":[{"name":"DePaul University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,12,27]]},"reference":[{"key":"e_1_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1889997.1889999"},{"key":"e_1_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1594835.1504203"},{"key":"e_1_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1787234.1787255"},{"key":"e_1_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.546611"},{"key":"e_1_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-33651-5_21"},{"key":"e_1_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627752"},{"key":"e_1_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-60225-7_4"},{"key":"e_1_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2484239.2484267"},{"key":"e_1_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-45174-8_26"},{"key":"e_1_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1926385.1926394"},{"key":"e_1_2_2_12_1","volume-title":"Deconstructing Transactions: The Subtleties of Atomicity. In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking.","author":"Blundell C.","year":"2005","unstructured":"C. Blundell , E. C. Lewis , and M. M. K. Martin . 2005 . Deconstructing Transactions: The Subtleties of Atomicity. In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking. C. Blundell, E. C. Lewis, and M. M. K. Martin. 2005. Deconstructing Transactions: The Subtleties of Atomicity. In Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking."},{"key":"e_1_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1375581.1375591"},{"key":"e_1_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485942"},{"key":"e_1_2_2_15_1","unstructured":"N. Chong T. Sorensen and J. Wickerson. 2017. The Semantics of Transactions and Weak Memory in x86 Power ARMv8 and C++. ArXiv e-prints (Oct. 2017). arXiv: cs.PL\/1710.04839  N. Chong T. Sorensen and J. Wickerson. 2017. The Semantics of Transactions and Weak Memory in x86 Power ARMv8 and C++. ArXiv e-prints (Oct. 2017). arXiv: cs.PL\/1710.04839"},{"key":"e_1_2_2_16_1","volume-title":"4th Workshop on Transactional Computing.","author":"Dalessandro L.","unstructured":"L. Dalessandro and M. L. Scott . 2009. Strong Isolation is a Weak Idea. In TRANSACT \u201909 : 4th Workshop on Transactional Computing. L. Dalessandro and M. L. Scott. 2009. Strong Isolation is a Weak Idea. In TRANSACT \u201909: 4th Workshop on Transactional Computing."},{"key":"e_1_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15763-9_4"},{"key":"e_1_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168917.1168900"},{"key":"e_1_2_2_19_1","unstructured":"W. Deacon. 2017. ARM64 cat file. https:\/\/github.com\/herd\/herdtools7\/commit\/daa126680b6ecba97ba47b3e05bbaa51a89f27b7 .  W. Deacon. 2017. ARM64 cat file. https:\/\/github.com\/herd\/herdtools7\/commit\/daa126680b6ecba97ba47b3e05bbaa51a89f27b7 ."},{"key":"e_1_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10181-1_21"},{"key":"e_1_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-41527-2_11"},{"key":"e_1_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2775435"},{"key":"e_1_2_2_23_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00165-012-0225-8"},{"key":"e_1_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-14720-8_1"},{"key":"e_1_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/360363.360369"},{"key":"e_1_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2837614.2837615"},{"key":"e_1_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1178597.1178609"},{"key":"e_1_2_2_28_1","unstructured":"D. Grossman V. Menon S. Srinivas and C. Zilles. 2007. Transactional Memory in Managed Runtimes - Hardware\/Software View. https:\/\/www.microarch.org\/micro40  D. Grossman V. Menon S. Srinivas and C. Zilles. 2007. Transactional Memory in Managed Runtimes - Hardware\/Software View. https:\/\/www.microarch.org\/micro40"},{"key":"e_1_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-87779-0_21"},{"key":"e_1_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345233"},{"key":"e_1_2_2_31_1","doi-asserted-by":"crossref","unstructured":"R. Guerraoui and M. Kapalka. 2010. Principles of Transactional Memory. Morgan & Claypool Publishers.  R. Guerraoui and M. Kapalka. 2010. Principles of Transactional Memory. Morgan & Claypool Publishers.","DOI":"10.1007\/978-3-031-02002-5"},{"key":"e_1_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/197320.197346"},{"key":"e_1_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53426-7_20"},{"key":"e_1_2_2_34_1","doi-asserted-by":"crossref","unstructured":"T. Harris J. Larus and R. Rajwar. 2010. Transactional Memory 2nd edition. Morgan & Claypool Publishers.  T. Harris J. Larus and R. Rajwar. 2010. Transactional Memory 2nd edition. Morgan & Claypool Publishers.","DOI":"10.1007\/978-3-031-01728-5"},{"key":"e_1_2_2_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065944.1065952"},{"key":"e_1_2_2_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_2_2_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/78969.78972"},{"key":"e_1_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.tcs.2012.04.037"},{"key":"e_1_2_2_39_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2005.03.001"},{"key":"e_1_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1583991.1584013"},{"key":"e_1_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.599898"},{"key":"e_1_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1364782.1364800"},{"key":"e_1_2_2_43_1","unstructured":"V. Luchangco J. Maurer M. Moir H. Boehm J. Gottschlich M. Michael T. Riegel M. Scott T. Shpeisman M. Spear and M. Wong. 2013. Transactional Memory Support for C++. http:\/\/www.open-std.org\/jtc1\/sc22\/wg21\/docs\/papers\/2013\/n3718. pdf  V. Luchangco J. Maurer M. Moir H. Boehm J. Gottschlich M. Michael T. Riegel M. Scott T. Shpeisman M. Spear and M. Wong. 2013. Transactional Memory Support for C++. http:\/\/www.open-std.org\/jtc1\/sc22\/wg21\/docs\/papers\/2013\/n3718. pdf"},{"key":"e_1_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.entcs.2007.04.009"},{"key":"e_1_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1040305.1040336"},{"key":"e_1_2_2_46_1","unstructured":"L. Maranget S. Sarkar and P. Sewell. 2012. A Tutorial Introduction to the ARM and POWER Relaxed Memory Models. http:\/\/www.cl.cam.ac.uk\/~pes20\/ppc-supplemental\/test7.pdf .  L. Maranget S. Sarkar and P. Sewell. 2012. A Tutorial Introduction to the ARM and POWER Relaxed Memory Models. http:\/\/www.cl.cam.ac.uk\/~pes20\/ppc-supplemental\/test7.pdf ."},{"key":"e_1_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1328438.1328448"},{"key":"e_1_2_2_48_1","unstructured":"A. T. Nguyen. 2015. Investigation of Hardware Transactional Memory. Master\u2019s thesis. MIT.  A. T. Nguyen. 2015. Investigation of Hardware Transactional Memory. Master\u2019s thesis. MIT."},{"key":"e_1_2_2_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1449764.1449780"},{"key":"e_1_2_2_50_1","doi-asserted-by":"crossref","unstructured":"C. Pulte S. Flur W. Deacon J. French S. Sarkar and P. Sewell. 2018. Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8. In POPL. To appear.  C. Pulte S. Flur W. Deacon J. French S. Sarkar and P. Sewell. 2018. Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8. In POPL. To appear.","DOI":"10.1145\/3158107"},{"key":"e_1_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993520"},{"key":"e_1_2_2_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/2789149.2789166"},{"key":"e_1_2_2_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785414.1785443"},{"key":"e_1_2_2_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/224964.224987"},{"key":"e_1_2_2_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/3009837.3009838"},{"key":"e_1_2_2_57_1","first-page":"1","article-title":"Performance evaluation of Intel\u00ae transactional synchronization extensions for high-performance computing. In SC, W. Gropp and S. Matsuoka (Eds.)","volume":"19","author":"Yoo R. M.","year":"2013","unstructured":"R. M. Yoo , C. J. Hughes , K. Lai , and R. Rajwar . 2013 . Performance evaluation of Intel\u00ae transactional synchronization extensions for high-performance computing. In SC, W. Gropp and S. Matsuoka (Eds.) . ACM , 19 : 1 \u2013 19 :11. R. M. Yoo, C. J. Hughes, K. Lai, and R. Rajwar. 2013. Performance evaluation of Intel\u00ae transactional synchronization extensions for high-performance computing. In SC, W. Gropp and S. Matsuoka (Eds.). ACM, 19:1\u201319:11.","journal-title":"ACM"}],"container-title":["Proceedings of the ACM on Programming Languages"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3158106","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3158106","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:30Z","timestamp":1750212690000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3158106"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12,27]]},"references-count":55,"journal-issue":{"issue":"POPL","published-print":{"date-parts":[[2018,1]]}},"alternative-id":["10.1145\/3158106"],"URL":"https:\/\/doi.org\/10.1145\/3158106","relation":{},"ISSN":["2475-1421"],"issn-type":[{"value":"2475-1421","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,12,27]]},"assertion":[{"value":"2017-12-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}