{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:16:37Z","timestamp":1758892597970,"version":"3.41.0"},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,12,22]],"date-time":"2017-12-22T00:00:00Z","timestamp":1513900800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2017,12,31]]},"abstract":"<jats:p>This article presents a new method for Monte Carlo (MC) option pricing using field-programmable gate arrays (FPGAs), which use a discrete-space random walk over a binomial lattice, rather than the continuous space-walks used by existing approaches. The underlying hypothesis is that the discrete-space walk will significantly reduce the area needed for each MC engine, and the resulting increase in parallelisation and raw performance outweighs any accuracy losses introduced by the discretisation. Experimental results support this hypothesis, showing that for a given MC simulation size, there is no significant loss in accuracy by using a discrete space model for the path-dependent exotic financial options. Analysis of the binomial simulation model shows that only limited-precision fixed-point arithmetic is needed, and also shows that pairs of MC kernels are able to share RAM resources. When using realistic constraints on pricing problems, it was found that the size of a discrete-space MC engine can be kept to 370 Flip-Flops and 233 Lookup Tables, allowing up to 3,000 variance-reduced MC cores in one FPGA. The combination of a highly parallelisable architecture and model-specific optimisations means that the binomial pricing technique allows for a 50\u00d7 improvement in throughput compared to existing FPGA approaches, without any reduction in accuracy.<\/jats:p>","DOI":"10.1145\/3158228","type":"journal-article","created":{"date-parts":[[2017,12,22]],"date-time":"2017-12-22T17:17:37Z","timestamp":1513963057000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Efficient Reconfigurable Architecture for Pricing Exotic Options"],"prefix":"10.1145","volume":"10","author":[{"given":"Pieter","family":"Fabry","sequence":"first","affiliation":[{"name":"Imperial College London, London, United Kingdom"}]},{"given":"David","family":"Thomas","sequence":"additional","affiliation":[{"name":"Imperial College London, London, United Kingdom"}]}],"member":"320","published-online":{"date-parts":[[2017,12,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.46"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1086\/260062"},{"key":"e_1_2_1_3_1","first-page":"320","article-title":"Variance reduction with control variate for pricing Asian options in a geometric levy model","volume":"41","author":"Boughamoura Wissem","year":"2011","journal-title":"IAENG Int. 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Binomial Trees in Option Pricing\u2014History Practical Applications and Recent Developments. Physica-Verlag HD Heidelberg 59--77.  Ralf Korn and Stefanie M\u00fcller. 2010. Binomial Trees in Option Pricing\u2014History Practical Applications and Recent Developments. Physica-Verlag HD Heidelberg 59--77.","DOI":"10.1007\/978-3-7908-2598-5_3"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.18637\/jss.v008.i14"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/SAAHPC.2012.21"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2007.4429975"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1926367.1926371"},{"volume-title":"Proceedings of the International Conference on Field-Programmable Technology (FPT\u201905)","author":"Zhang G. L.","key":"e_1_2_1_19_1"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3158228","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3158228","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:13:23Z","timestamp":1750212803000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3158228"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12,22]]},"references-count":19,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,12,31]]}},"alternative-id":["10.1145\/3158228"],"URL":"https:\/\/doi.org\/10.1145\/3158228","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2017,12,22]]},"assertion":[{"value":"2017-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-11-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-12-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}