{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T16:28:33Z","timestamp":1770740913145,"version":"3.49.0"},"reference-count":49,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2018,1,26]],"date-time":"2018-01-26T00:00:00Z","timestamp":1516924800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"DARPA\/CMO","award":["HR0011-13-C-0005"],"award-info":[{"award-number":["HR0011-13-C-0005"]}]},{"name":"Leggett Family Fellowship"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2018,3,31]]},"abstract":"<jats:p>We show that continuously monitoring on-chip delays at the LUT-to-LUT link level during operation allows a field-programmable gate array to detect and self-adapt to aging and environmental timing effects. Using a lightweight (&lt;4% added area) mechanism for monitoring transition timing, a Difference Detector with First-Fail Latch, we can estimate the timing margin on circuits and identify the individual links that have degraded and whose delay is determining the worst-case circuit delay. Combined with Choose-Your-own-Adventure precomputed, fine-grained repair alternatives, we introduce a strategy for rapid, in-system incremental repair of links with degraded timing. We show that these techniques allow us to respond to a single aging event in less than 190ms for the toronto20 benchmarks. The result is a step toward systems where adaptive reconfiguration on the time-scale of seconds is viable and beneficial.<\/jats:p>","DOI":"10.1145\/3158229","type":"journal-article","created":{"date-parts":[[2018,1,29]],"date-time":"2018-01-29T13:48:05Z","timestamp":1517233685000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)"],"prefix":"10.1145","volume":"11","author":[{"given":"Hans","family":"Giesen","sequence":"first","affiliation":[{"name":"University of Pennsylvania"}]},{"given":"Benjamin","family":"Gojman","sequence":"additional","affiliation":[{"name":"University of Pennsylvania"}]},{"given":"Raphael","family":"Rubin","sequence":"additional","affiliation":[{"name":"University of Pennsylvania"}]},{"given":"Ji","family":"Kim","sequence":"additional","affiliation":[{"name":"University of Pennsylvania"}]},{"given":"Andr\u00e9","family":"Dehon","sequence":"additional","affiliation":[{"name":"University of Pennsylvania"}]}],"member":"320","published-online":{"date-parts":[[2018,1,26]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the International Symposium on Quality Electronic Design. 238--243","author":"Alam Syed M.","unstructured":"Syed M. Alam , Gan Chee Lip , Carl V. Thompson , and Donald E. Troxel . 2004. Circuit level reliability analysis of Cu interconnects . In Proceedings of the International Symposium on Quality Electronic Design. 238--243 . Syed M. Alam, Gan Chee Lip, Carl V. Thompson, and Donald E. Troxel. 2004. Circuit level reliability analysis of Cu interconnects. In Proceedings of the International Symposium on Quality Electronic Design. 238--243."},{"key":"e_1_2_1_2_1","unstructured":"Altera. 2005. Implementing PLL Reconfiguration in Stratix 8 Stratix GX Devices (AN282). Retrieved from https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/an\/an282.pdf.  Altera. 2005. Implementing PLL Reconfiguration in Stratix 8 Stratix GX Devices (AN282). Retrieved from https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/an\/an282.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274005"},{"key":"e_1_2_1_4_1","unstructured":"Vaughn Betz and Jonathan Rose. 1999. FPGA Place-and-Route Challenge. Retrieved from http:\/\/www.eecg.toronto.edu\/&sim;vaughn\/challenge\/challenge.html.  Vaughn Betz and Jonathan Rose. 1999. FPGA Place-and-Route Challenge. Retrieved from http:\/\/www.eecg.toronto.edu\/&sim;vaughn\/challenge\/challenge.html."},{"key":"e_1_2_1_5_1","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"Betz Vaughn","unstructured":"Vaughn Betz , Jonathan Rose , and Alexander Marquardt . 1999. Architecture and CAD for Deep-Submicron FPGAs . Kluwer Academic Publishers , Norwell, MA . Vaughn Betz, Jonathan Rose, and Alexander Marquardt. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Norwell, MA."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005413"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.24"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology. 173--180","author":"Chow C. T.","unstructured":"C. T. Chow , L. S. M. Tsui , Philip H. W. Leong , Wayne Luk , and Steve J. E. Wilton . 2005. Dynamic voltage scaling for commercial FPGAs . In Proceedings of the International Conference on Field-Programmable Technology. 173--180 . C. T. Chow, L. S. M. Tsui, Philip H. W. Leong, Wayne Luk, and Steve J. E. Wilton. 2005. Dynamic voltage scaling for commercial FPGAs. In Proceedings of the International Conference on Field-Programmable Technology. 173--180."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the FAA\/NASA\/DoD Joint Council on Aging Aircraft Conf.","author":"Condra Lloyd","unstructured":"Lloyd Condra , J. Qin , and Joseph B. Bernstein . 2007. State of the art semiconductor devices in future aerospace systems . In Proceedings of the FAA\/NASA\/DoD Joint Council on Aging Aircraft Conf. Lloyd Condra, J. Qin, and Joseph B. Bernstein. 2007. State of the art semiconductor devices in future aerospace systems. In Proceedings of the FAA\/NASA\/DoD Joint Council on Aging Aircraft Conf."},{"key":"e_1_2_1_10_1","volume-title":"Elements of Information Theory","author":"Cover Thomas","unstructured":"Thomas Cover and Joy Thomas . 1991. Elements of Information Theory . John Wiley and Sons, Inc. , New York . Thomas Cover and Joy Thomas. 1991. Elements of Information Theory. John Wiley and Sons, Inc., New York."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718323"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508145"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.36"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3026124"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the International Conference on Field-Programmable Technology. 229--234","author":"Jeffrey","unstructured":"Jeffrey B. Goeders and Steven J. E. Wilton. 2012. VersaPower: Power estimation for diverse FPGA architectures . In Proceedings of the International Conference on Field-Programmable Technology. 229--234 . Jeffrey B. Goeders and Steven J. E. Wilton. 2012. VersaPower: Power estimation for diverse FPGA architectures. In Proceedings of the International Conference on Field-Programmable Technology. 229--234."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650352"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597889"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1080\/00401706.1970.10488630"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650393"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393249"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554784"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.27"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508135"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611821"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435292"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270315"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847334"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/647926.739234"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.2307\/3607889"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145710"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2100531"},{"key":"e_1_2_1_35_1","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/16.725248","article-title":"A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs","volume":"45","author":"Renn Shing-Hwa","year":"1998","unstructured":"Shing-Hwa Renn , Christine Raynaud , Jean-Luc Pelloie , and Francis Balestra . 1998 . A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs . IEEE Trans. Electron. Dev. 45 , 10 (October 1998), 2146--2152. Shing-Hwa Renn, Christine Raynaud, Jean-Luc Pelloie, and Francis Balestra. 1998. A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs. IEEE Trans. Electron. Dev. 45, 10 (October 1998), 2146--2152.","journal-title":"IEEE Trans. Electron. Dev."},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.75006"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1989.74291"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068719"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1567461"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.641688"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795909"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70235"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723152"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770808"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1534916.1534920"},{"key":"e_1_2_1_46_1","unstructured":"Xilinx. 2015. UltraScale Architecture and Product Overview (DS890). Retrieved from http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds890-ultrascale-overview.pdf.  Xilinx. 2015. UltraScale Architecture and Product Overview (DS890). Retrieved from http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds890-ultrascale-overview.pdf."},{"key":"e_1_2_1_47_1","unstructured":"Xilinx Inc. 2008. Virtex-5 FPGA Configuration User Guide. Xilinx Inc. 2100 Logic Drive San Jose CA 95124. UG191 Retrieved from http:\/\/www.xilinx.com\/bvdocs\/userguides\/ug191.pdf.  Xilinx Inc. 2008. Virtex-5 FPGA Configuration User Guide. Xilinx Inc. 2100 Logic Drive San Jose CA 95124. UG191 Retrieved from http:\/\/www.xilinx.com\/bvdocs\/userguides\/ug191.pdf."},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723153"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3158229","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3158229","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:13:23Z","timestamp":1750212803000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3158229"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1,26]]},"references-count":49,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2018,3,31]]}},"alternative-id":["10.1145\/3158229"],"URL":"https:\/\/doi.org\/10.1145\/3158229","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,1,26]]},"assertion":[{"value":"2016-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-01-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}