{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:56:23Z","timestamp":1750308983104,"version":"3.41.0"},"reference-count":10,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,11,22]],"date-time":"2017-11-22T00:00:00Z","timestamp":1511308800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGBED Rev."],"published-print":{"date-parts":[[2017,11,22]]},"abstract":"<jats:p>A heterogeneous network, where a switched-Ethernet backbone, e.g. AFDX, interconnects several end systems based on Network-on-Chip (NoC), is a promising candidate to build new avionics architectures. When using such a heterogeneous network for real-time applications, a global worst-case traversal time (WCTT) analysis is needed. In this short paper we focus on the intra-NoC communication on a Tilera TILE64-like NoC. First, we extend the Recursive Calculus (RC) to achieve tighter intra-NoC WCTT. Then, we explain how this intra-NoC WCTT analysis could be used in a compositional manner for the end-to-end inter-NoC delay analysis.<\/jats:p>","DOI":"10.1145\/3166227.3166232","type":"journal-article","created":{"date-parts":[[2017,11,27]],"date-time":"2017-11-27T13:24:24Z","timestamp":1511789064000},"page":"35-37","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Extended recursive analysis for tilera tile64 NoC architectures"],"prefix":"10.1145","volume":"14","author":[{"given":"Hamdi","family":"Ayed","sequence":"first","affiliation":[{"name":"Toulouse University, Toulouse, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-luc","family":"Scharbarg","sequence":"additional","affiliation":[{"name":"Toulouse University, Toulouse, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J\u00e9r\u00f4me","family":"Ermont","sequence":"additional","affiliation":[{"name":"Toulouse University, Toulouse, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Fraboul","sequence":"additional","affiliation":[{"name":"Toulouse University, Toulouse, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,11,22]]},"reference":[{"volume-title":"Industrial Embedded Systems (SIES), 2015 10th IEEE International Symposium on. 1--10","author":"Abdallah L.","key":"e_1_2_1_1_1","unstructured":"L. Abdallah , M. Jan , J. Ermont , and C. Fraboul . 2015. Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores . In Industrial Embedded Systems (SIES), 2015 10th IEEE International Symposium on. 1--10 . L. Abdallah, M. Jan, J. Ermont, and C. Fraboul. 2015. Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores. In Industrial Embedded Systems (SIES), 2015 10th IEEE International Symposium on. 1--10."},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"L. Abdallah M. Jan J. Ermont and C. Fraboul. 2016. Reducing the Contention Experienced by Real-Time Core-to-I\/O Flows over a Tilera-Like Network on Chip. ECRTS (2016) 86--96.  L. Abdallah M. Jan J. Ermont and C. Fraboul. 2016. Reducing the Contention Experienced by Real-Time Core-to-I\/O Flows over a Tilera-Like Network on Chip. ECRTS (2016) 86--96.","DOI":"10.1109\/ECRTS.2016.9"},{"volume-title":"2016 IEEE World Conference on Factory Communication Systems (WFCS). 1--4.","author":"Ayed H.","key":"e_1_2_1_3_1","unstructured":"H. Ayed , J. Ermont , J. l. Scharbarg , and C. Fraboul . 2016. Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures . In 2016 IEEE World Conference on Factory Communication Systems (WFCS). 1--4. H. Ayed, J. Ermont, J. l. Scharbarg, and C. Fraboul. 2016. Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures. In 2016 IEEE World Conference on Factory Communication Systems (WFCS). 1--4."},{"key":"e_1_2_1_4_1","volume-title":"Work in Progress Session of the 28th Euromicro Conference on Real-Time Systems (ECRTS","author":"Ayed Hamdi","year":"2016","unstructured":"Hamdi Ayed , J\u00e9r\u00f4me Ermont , Jean-Luc Scharbarg , and Christian Fraboul . 2016 . Tightening worst-case timing analysis of Tilera-like NoC architectures . In Work in Progress Session of the 28th Euromicro Conference on Real-Time Systems (ECRTS 2016). Hamdi Ayed, J\u00e9r\u00f4me Ermont, Jean-Luc Scharbarg, and Christian Fraboul. 2016. Tightening worst-case timing analysis of Tilera-like NoC architectures. In Work in Progress Session of the 28th Euromicro Conference on Real-Time Systems (ECRTS 2016)."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2010.2055877"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2567937"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/SIES.2009.5196187"},{"volume-title":"Proceedings of the 3rd European Congress Embedded Real Time Software, Toulouse.","author":"Frances F.","key":"e_1_2_1_8_1","unstructured":"F. Frances , C. Fraboul , and J. Grieu . 2006. Using Network Calculus to optimize the AFDX Network . Proceedings of the 3rd European Congress Embedded Real Time Software, Toulouse. F. Frances, C. Fraboul, and J. Grieu. 2006. Using Network Calculus to optimize the AFDX Network. Proceedings of the 3rd European Congress Embedded Real Time Software, Toulouse."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1740954.1741051"},{"key":"e_1_2_1_10_1","volume-title":"7th IEEE International Symposium on Industrial Embedded Systems","author":"Li X.","year":"2012","unstructured":"X. Li , J. L. Scharbarg , and C. Fraboul . 2012. Worst case delay analysis on a real-time heterogeneous network . 7th IEEE International Symposium on Industrial Embedded Systems ( 2012 ). X. Li, J. L. Scharbarg, and C. Fraboul. 2012. Worst case delay analysis on a real-time heterogeneous network. 7th IEEE International Symposium on Industrial Embedded Systems (2012)."}],"container-title":["ACM SIGBED Review"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3166227.3166232","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3166227.3166232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:41:06Z","timestamp":1750282866000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3166227.3166232"}},"subtitle":["towards inter-NoC delay analysis"],"short-title":[],"issued":{"date-parts":[[2017,11,22]]},"references-count":10,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,11,22]]}},"alternative-id":["10.1145\/3166227.3166232"],"URL":"https:\/\/doi.org\/10.1145\/3166227.3166232","relation":{},"ISSN":["1551-3688"],"issn-type":[{"type":"electronic","value":"1551-3688"}],"subject":[],"published":{"date-parts":[[2017,11,22]]},"assertion":[{"value":"2017-11-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}