{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:35:06Z","timestamp":1750221306314,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,4,9]],"date-time":"2018-04-09T00:00:00Z","timestamp":1523232000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Spanish Ministry of Education, Culture and Sports","award":["FPU15\/01394"],"award-info":[{"award-number":["FPU15\/01394"]}]},{"name":"Spanish Ministry of Economy and Competitiveness","award":["TIN2015-65316-P,TIN2014-60404-JIN,RYC-2013-14717"],"award-info":[{"award-number":["TIN2015-65316-P,TIN2014-60404-JIN,RYC-2013-14717"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,4,9]]},"DOI":"10.1145\/3167132.3167197","type":"proceedings-article","created":{"date-parts":[[2018,7,3]],"date-time":"2018-07-03T13:54:10Z","timestamp":1530626050000},"page":"593-600","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["RPR"],"prefix":"10.1145","author":[{"given":"Pedro","family":"Benedicte","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center (BSC) and Universitat Polit\u00e8cnica de Catalunya (UPC)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carles","family":"Hernandez","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center (BSC) and IIIA-CSIC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"J. Abella etal 2014. Heart of Gold: Making the Improbable Happen to Extend Coverage in Probabilistic Timing Analysis. In ECRTS.  J. Abella et al. 2014. Heart of Gold: Making the Improbable Happen to Extend Coverage in Probabilistic Timing Analysis. In ECRTS.","DOI":"10.1109\/ECRTS.2014.33"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"J. Abella etal 2015. WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness. In SIES.  J. Abella et al. 2015. WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness. In SIES.","DOI":"10.1109\/SIES.2015.7185039"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3065924"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2015.26"},{"key":"e_1_3_2_1_5_1","unstructured":"P. Alfke. 1996. Efficient Shift Registers LFSR Counters and Long Pseudo-Random Sequence Generators. Xilinx.  P. Alfke. 1996. Efficient Shift Registers LFSR Counters and Long Pseudo-Random Sequence Generators. Xilinx."},{"key":"e_1_3_2_1_6_1","unstructured":"ARM. 2006. Cortex-R4 and Cortex-R4F Technical Reference Manual.  ARM. 2006. Cortex-R4 and Cortex-R4F Technical Reference Manual."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"e_1_3_2_1_8_1","unstructured":"D. Buttle. 2012. ETAS GmbH Germany Real-Time in the Prime-Time. Keynote talk.. In ECRTS.  D. Buttle. 2012. ETAS GmbH Germany Real-Time in the Prime-Time. Keynote talk.. In ECRTS."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669164"},{"key":"e_1_3_2_1_10_1","unstructured":"T. Chen P. Liu and K.C. Stelzer. 2006. Implementation of a pseudo-LRU algorithm in a partitioned cache. (2006). US Patent number 7 069 390.  T. Chen P. Liu and K.C. Stelzer. 2006. Implementation of a pseudo-LRU algorithm in a partitioned cache. (2006). US Patent number 7 069 390."},{"key":"e_1_3_2_1_11_1","unstructured":"COBHAM. {n. d.}. LEON3 Processor. Probabilistic platform. http:\/\/www.gaisler.com\/index.php\/products\/processors\/leon3. ({n. d.}).  COBHAM. {n. d.}. LEON3 Processor. Probabilistic platform. http:\/\/www.gaisler.com\/index.php\/products\/processors\/leon3. ({n. d.})."},{"key":"e_1_3_2_1_12_1","unstructured":"Cobham Gaisler. 2011. Quad Core LEON4 SPARC V8 Processor - LEON4-NGMP-DRAFT - Data Sheet and Users Manual.  Cobham Gaisler. 2011. Quad Core LEON4 SPARC V8 Processor - LEON4-NGMP-DRAFT - Data Sheet and Users Manual."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.31"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531084"},{"key":"e_1_3_2_1_15_1","unstructured":"Esterel Technologies SA. 2006. Efficient Developement of Safe Avionics Software with DO-178B Objectives Using SCADE Suite - Methodological Handbook.  Esterel Technologies SA. 2006. Efficient Developement of Safe Avionics Software with DO-178B Objectives Using SCADE Suite - Methodological Handbook."},{"key":"e_1_3_2_1_16_1","unstructured":"Manual. Rev. 5. Freescale Semiconductor. 2005 MPC7450 RISC Microprocessor Family Reference"},{"key":"e_1_3_2_1_17_1","volume-title":"Present and Future. In WCET Workshop.","author":"Gustafsson J.","year":"2010","unstructured":"J. Gustafsson 2010 . The M\u00e4lardalen WCET Benchmarks-Past , Present and Future. In WCET Workshop. J. Gustafsson et al. 2010. The M\u00e4lardalen WCET Benchmarks-Past, Present and Future. In WCET Workshop."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898076"},{"key":"e_1_3_2_1_19_1","unstructured":"International Electrotechnical Comission. 2009. IEC 61508 Functional Safety of Electrical\/Electronic\/Programmable Electronic Safety-related Systems Edition 2.0.  International Electrotechnical Comission. 2009. IEC 61508 Functional Safety of Electrical\/Electronic\/Programmable Electronic Safety-related Systems Edition 2.0."},{"key":"e_1_3_2_1_20_1","unstructured":"International Organization for Standardization. 2009. ISO\/DIS 26262. Road Vehicles - Functional Safety.  International Organization for Standardization. 2009. ISO\/DIS 26262. Road Vehicles - Functional Safety."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"J. Jalle etal 2014. Bus Designs for Time-Probabilistic Multicore Processors. In DATE.   J. Jalle et al. 2014. Bus Designs for Time-Probabilistic Multicore Processors. In DATE.","DOI":"10.7873\/DATE.2014.063"},{"key":"e_1_3_2_1_23_1","unstructured":"J. Jalle etal 2016. Validating a Timing Simulator for the NGMP Multicore Processor. In DASIA.  J. Jalle et al. 2016. Validating a Timing Simulator for the NGMP Multicore Processor. In DASIA."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.268884"},{"key":"e_1_3_2_1_25_1","unstructured":"L. Kosmidis D. Compagnin D. Morales E. Mezzetti E. Qui\u00f1ones J. Abella Tullio Vardanega and F.J. Cazorla. 2016. Measurement-Based Timing Analysis of the AURIX Caches. In WCET.  L. Kosmidis D. Compagnin D. Morales E. Mezzetti E. Qui\u00f1ones J. Abella Tullio Vardanega and F.J. Cazorla. 2016. Measurement-Based Timing Analysis of the AURIX Caches. In WCET."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967078"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"L. Kosmidis etal 2013. A Cache Design for Probabilistically Analysable Real-time Systems. In DATE.   L. Kosmidis et al. 2013. A Cache Design for Probabilistically Analysable Real-time Systems. In DATE.","DOI":"10.7873\/DATE.2013.116"},{"key":"e_1_3_2_1_28_1","volume-title":"Probabilistic Timing Analysis on Conventional Cache Designs. In DATE.","author":"Kosmidis L.","year":"2013","unstructured":"L. Kosmidis 2013 . Probabilistic Timing Analysis on Conventional Cache Designs. In DATE. L. Kosmidis et al. 2013. Probabilistic Timing Analysis on Conventional Cache Designs. In DATE."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","unstructured":"S. Kotz and S. Nadarajah. 2000. Extreme value distributions: theory and applications. World Scientific. 185 pages.  S. Kotz and S. Nadarajah. 2000. Extreme value distributions: theory and applications. World Scientific. 185 pages.","DOI":"10.1142\/p191"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378252"},{"key":"e_1_3_2_1_31_1","unstructured":"P. Machado etal 2017. Probabilistic Timing Analysis on Time-Randomized Platforms for the Space Domain. In DATE.   P. Machado et al. 2017. Probabilistic Timing Analysis on Time-Randomized Platforms for the Space Domain. In DATE."},{"key":"e_1_3_2_1_32_1","unstructured":"J. Owens. 2015. Delphi Automotive The Design of Innovation That Drives Tomorrow. Keynote talk.. In DAC.  J. Owens. 2015. Delphi Automotive The Design of Innovation That Drives Tomorrow. Keynote talk.. In DAC."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_34_1","unstructured":"SoCLib. 2003-2012. -. (2003-2012). http:\/\/www.soclib.fr\/trac\/dev.  SoCLib. 2003-2012. -. (2003-2012). http:\/\/www.soclib.fr\/trac\/dev."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"Z. Stephenson J. Abella and T. Vardanega. 2013. Supporting Industrial Use of Probabilistic Timing Analysis with Explicit Argumentation. In INDIN.  Z. Stephenson J. Abella and T. Vardanega. 2013. Supporting Industrial Use of Probabilistic Timing Analysis with Explicit Argumentation. In INDIN.","DOI":"10.1109\/INDIN.2013.6622975"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"F. Wartel etal 2013. Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study. In SIES.  F. Wartel et al. 2013. Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study. In SIES.","DOI":"10.1109\/SIES.2013.6601497"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"crossref","unstructured":"F. Wartel etal 2015. Timing Analysis of an Avionics Case Study on Complex Hardware\/Software Platforms. In DATE.   F. Wartel et al. 2015. Timing Analysis of an Avionics Case Study on Complex Hardware\/Software Platforms. In DATE.","DOI":"10.7873\/DATE.2015.0189"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"}],"event":{"name":"SAC 2018: Symposium on Applied Computing","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"],"location":"Pau France","acronym":"SAC 2018"},"container-title":["Proceedings of the 33rd Annual ACM Symposium on Applied Computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3167132.3167197","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3167132.3167197","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:13:29Z","timestamp":1750212809000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3167132.3167197"}},"subtitle":["a random replacement policy with limited pathological replacements"],"short-title":[],"issued":{"date-parts":[[2018,4,9]]},"references-count":38,"alternative-id":["10.1145\/3167132.3167197","10.1145\/3167132"],"URL":"https:\/\/doi.org\/10.1145\/3167132.3167197","relation":{},"subject":[],"published":{"date-parts":[[2018,4,9]]},"assertion":[{"value":"2018-04-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}