{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:48:13Z","timestamp":1772164093919,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":74,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,3,19]],"date-time":"2018-03-19T00:00:00Z","timestamp":1521417600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,3,19]]},"DOI":"10.1145\/3173162.3177158","type":"proceedings-article","created":{"date-parts":[[2018,3,22]],"date-time":"2018-03-22T11:15:40Z","timestamp":1521717340000},"page":"43-55","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Slim NoC"],"prefix":"10.1145","author":[{"given":"Maciej","family":"Besta","sequence":"first","affiliation":[{"name":"ETH Z\u00fcrich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Syed Minhaj","family":"Hassan","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhakar","family":"Yalamanchili","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rachata","family":"Ausavarungnirun","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich&amp;Carnegie Mellon University, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Torsten","family":"Hoefler","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,3,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522344"},{"key":"e_1_3_2_1_2_1","author":"Agerwala T.","year":"1995","unstructured":"T. Agerwala , J. Martin , J. Mirza , D. Sadler , D. Dias , and M. Snir . SP2 System Architecture. IBM Systems Journal , 1995 . T. Agerwala, J. Martin, J. Mirza, D. Sadler, D. Dias, and M. Snir. SP2 System Architecture. IBM Systems Journal, 1995.","journal-title":"SP2 System Architecture. IBM Systems Journal"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654101"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2512433"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2010.23"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2014.31"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2016.01.009"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_3_2_1_10_1","volume-title":"Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy-Efficiency and Scalability. Technical report","author":"Besta M.","year":"2017","unstructured":"M. Besta , S. M. Hassan , S. Yalamanchili , R. Ausavarungnirun , O. Mutlu , and T. Hoefler . Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy-Efficiency and Scalability. Technical report , 2017 . M. Besta, S. M. Hassan, S. Yalamanchili, R. Ausavarungnirun, O. Mutlu, and T. Hoefler. Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy-Efficiency and Scalability. Technical report, 2017."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.34"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2015.7085472"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831831"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2012.44"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485371"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522333"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.63"},{"key":"e_1_3_2_1_19_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W.","year":"2003","unstructured":"W. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers Inc ., 2003 . W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798252"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669150"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815976"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"crossref","DOI":"10.1137\/1.9781611971811","volume-title":"LINPACK Users' Guide","author":"Dongarra J. J.","year":"1979","unstructured":"J. J. Dongarra , C. B. Moler , J. R. Bunch , and G. W. Stewart . LINPACK Users' Guide . SIAM , 1979 . J. J. Dongarra, C. B. Moler, J. R. Bunch, and G. W. Stewart. LINPACK Users' Guide. SIAM, 1979."},{"key":"e_1_3_2_1_24_1","unstructured":"EZchip Semiconductor Ltd. EZchip Introduces TILE-Mx100 World's Highest Core-Count ARM Processor Optimized for High-Performance Networking Applications. http:\/\/www.tilera.com\/News\/PressRelease\/?ezchip=97 2015.  EZchip Semiconductor Ltd. EZchip Introduces TILE-Mx100 World's Highest Core-Count ARM Processor Optimized for High-Performance Networking Applications. http:\/\/www.tilera.com\/News\/PressRelease\/?ezchip=97 2015."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014903"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.8"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-8274-1_10"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-016-5588-7"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798251"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000112"},{"key":"e_1_3_2_1_31_1","volume-title":"Low Power Router for High Radix NoCs. NOCS","author":"Hassan S.","year":"2013","unstructured":"S. Hassan and S. Yalamanchili . Centralized Buffer Router: A Low Latency , Low Power Router for High Radix NoCs. NOCS , 2013 . S. Hassan and S. Yalamanchili. Centralized Buffer Router: A Low Latency, Low Power Router for High Radix NoCs. NOCS, 2013."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2014.7008770"},{"key":"e_1_3_2_1_33_1","volume-title":"User's Manual for CPLEX, v12.1","author":"IBM","year":"2009","unstructured":"IBM ILOG. User's Manual for CPLEX, v12.1 . International Business Machines Corporation , 2009 . IBM ILOG. User's Manual for CPLEX, v12.1. International Business Machines Corporation, 2009."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.5555\/2691365.2691424"},{"key":"e_1_3_2_1_35_1","volume-title":"Booksim 2.0 User's Guide","author":"Jiang N.","year":"2010","unstructured":"N. Jiang , G. Michelogiannakis , D. Becker , B. Towles , and W. J. Dally . Booksim 2.0 User's Guide . Standford University , 2010 . N. Jiang, G. Michelogiannakis, D. Becker, B. Towles, and W. J. Dally. Booksim 2.0 User's Guide. Standford University, 2010."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2164538"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669145"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250679"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.19"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.14"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.18"},{"key":"e_1_3_2_1_42_1","volume-title":"IEEE TC","author":"Leiserson C. E.","year":"1985","unstructured":"C. E. Leiserson . Fat-Trees : Universal Networks for Hardware-Efficient Supercomputing . IEEE TC , 1985 . C. E. Leiserson. Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing. IEEE TC, 1985."},{"key":"e_1_3_2_1_43_1","volume-title":"CSS","author":"Liu J.","year":"2007","unstructured":"J. Liu and J. G. Delgado-Frias . A DAMQ Shared Buffer Scheme for Network-on-Chip . CSS , 2007 . J. Liu and J. G. Delgado-Frias. A DAMQ Shared Buffer Scheme for Network-on-Chip. CSS, 2007."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.05.005"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1006\/jctb.1998.1828"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798250"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.50"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1868447.1868459"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2342356.2342436"},{"key":"e_1_3_2_1_51_1","volume-title":"A 1024 Processor 64-bit RISC System-on-Chip. arXiv preprint arXiv:1610.01832","author":"Olofsson A.","year":"2016","unstructured":"A. Olofsson . Epiphany-V : A 1024 Processor 64-bit RISC System-on-Chip. arXiv preprint arXiv:1610.01832 , 2016 . A. Olofsson. Epiphany-V: A 1024 Processor 64-bit RISC System-on-Chip. arXiv preprint arXiv:1610.01832, 2016."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555808"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876446"},{"key":"e_1_3_2_1_54_1","unstructured":"Pezy Computing. PEZY-SC2. http:\/\/pezy.jp.  Pezy Computing. PEZY-SC2. http:\/\/pezy.jp."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/140901.141867"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.5555\/850940.852882"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.17"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.40"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.5555\/2616606.2616900"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193936"},{"key":"e_1_3_2_1_63_1","volume-title":"Dijkstra's algorithm. Implementing Discrete Mathematics: Combinatorics and Graph Theory with Mathematica","author":"Skiena S.","year":"1990","unstructured":"S. Skiena . Dijkstra's algorithm. Implementing Discrete Mathematics: Combinatorics and Graph Theory with Mathematica . Addison-Wesley , 1990 . S. Skiena. Dijkstra's algorithm. Implementing Discrete Mathematics: Combinatorics and Graph Theory with Mathematica. Addison-Wesley, 1990."},{"key":"e_1_3_2_1_64_1","volume-title":"HCS","author":"Sodani A.","year":"2015","unstructured":"A. Sodani . Knights Landing (KNL) : 2nd Generation Intel\u00ae Xeon Phi Processor . HCS , 2015 . A. Sodani. Knights Landing (KNL): 2nd Generation Intel\u00ae Xeon Phi Processor. HCS, 2015."},{"key":"e_1_3_2_1_65_1","volume-title":"MA","author":"Strang G.","year":"1993","unstructured":"G. Strang . Introduction to Linear Algebra . Wellesley-Cambridge Press Wellesley , MA , 1993 . G. Strang. Introduction to Linear Algebra. Wellesley-Cambridge Press Wellesley, MA, 1993."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.144624"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081402"},{"key":"e_1_3_2_1_69_1","volume-title":"Bus-Based On-Chip Networks. HPCA","author":"Udipi A. N.","year":"2010","unstructured":"A. N. Udipi , N. Muralimanohar , and R. Balasubramonian . Towards Scalable, Energy-Efficient , Bus-Based On-Chip Networks. HPCA , 2010 . A. N. Udipi, N. Muralimanohar, and R. Balasubramonian. Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks. HPCA, 2010."},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844466"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/2464996.2465436"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753327"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079090"},{"key":"e_1_3_2_1_74_1","volume-title":"HPCA","author":"Xu Y.","year":"2009","unstructured":"Y. Xu , Y. Du , B. Zhao , X. Zhou , Y. Zhang , and J. Yang . A Low-Radix and Low-Diameter 3D Interconnection Network Design . HPCA , 2009 . Y. Xu, Y. Du, B. Zhao, X. Zhou, Y. Zhang, and J. Yang. A Low-Radix and Low-Diameter 3D Interconnection Network Design. HPCA, 2009."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.19"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.27"}],"event":{"name":"ASPLOS '18: Architectural Support for Programming Languages and Operating Systems","location":"Williamsburg VA USA","acronym":"ASPLOS '18","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3173162.3177158","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3173162.3177158","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:26:23Z","timestamp":1750199183000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3173162.3177158"}},"subtitle":["A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability"],"short-title":[],"issued":{"date-parts":[[2018,3,19]]},"references-count":74,"alternative-id":["10.1145\/3173162.3177158","10.1145\/3173162"],"URL":"https:\/\/doi.org\/10.1145\/3173162.3177158","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/3296957.3177158","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2018,3,19]]},"assertion":[{"value":"2018-03-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}