{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:07:10Z","timestamp":1750306030056,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2018,4,30]],"date-time":"2018-04-30T00:00:00Z","timestamp":1525046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-0435060, CCR-0325197 and EN-CS-0329609"],"award-info":[{"award-number":["CNS-0435060, CCR-0325197 and EN-CS-0329609"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2018,4,30]]},"abstract":"<jats:p>Protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. However, advanced reverse engineering techniques can physically disassemble the chip and derive the IPs at a much lower cost than the value of IP design that chips carry. This invasive hardware attack\u2014obtaining information from IC chips\u2014always violates the IP rights of vendors. The intent of this article is to present a chip-level reverse engineering resilient design technique. In the proposed technique, transformable interconnects enable an IC chip to maintain functioning in normal use and to transform its physical structure into another pattern when exposed to invasive attacks. The newly created pattern will significantly increase the difficulty of reverse engineering. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead.<\/jats:p>","DOI":"10.1145\/3173462","type":"journal-article","created":{"date-parts":[[2018,7,26]],"date-time":"2018-07-26T11:58:04Z","timestamp":1532606284000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["A Chip-Level Anti-Reverse Engineering Technique"],"prefix":"10.1145","volume":"14","author":[{"given":"Shuai","family":"Chen","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junlin","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,7,25]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1558607.1558671"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the International Conference on USENIX Security. Boston MA, 291--306","author":"Alkabani Yousra","year":"2007","unstructured":"Yousra Alkabani and Farinaz Koushanfar . 2007 . Active hardware metering for intellectual property protection and security . In Proceedings of the International Conference on USENIX Security. Boston MA, 291--306 . Yousra Alkabani and Farinaz Koushanfar. 2007. Active hardware metering for intellectual property protection and security. In Proceedings of the International Conference on USENIX Security. Boston MA, 291--306."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/1326073.1326215"},{"issue":"6","key":"e_1_2_1_4_1","first-page":"289","article-title":"Intelligent agent for identifying intellectual property infringement issues in computer network sites and method of operation thereof. (Sept. 11 2001)","author":"Barney Matthew F.","year":"2001","unstructured":"Matthew F. Barney . 2001 . Intelligent agent for identifying intellectual property infringement issues in computer network sites and method of operation thereof. (Sept. 11 2001) . Patent No. 6 , 289 ,341. Matthew F. Barney. 2001. Intelligent agent for identifying intellectual property infringement issues in computer network sites and method of operation thereof. (Sept. 11 2001). Patent No. 6,289,341.","journal-title":"Patent"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.110624"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509456.1509604"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2015.7315145"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/77.919810"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2602554"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2013.6653606"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2098131"},{"issue":"5","key":"e_1_2_1_13_1","first-page":"635","article-title":"Simplified dual damascene process for multi-level metallization and interconnection structure. (June 3 1997)","author":"Huang Richard J.","year":"1997","unstructured":"Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , and Ming-Ren Lin . 1997 . Simplified dual damascene process for multi-level metallization and interconnection structure. (June 3 1997) . Patent No. 5 , 635 ,423. Richard J. Huang, Angela Hui, Robin Cheung, Mark Chang, and Ming-Ren Lin. 1997. Simplified dual damascene process for multi-level metallization and interconnection structure. (June 3 1997). Patent No. 5,635,423.","journal-title":"Patent"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1002\/adfm.201300127"},{"volume-title":"Foundations of Hardware IP Protection","author":"Jung Edward","key":"e_1_2_1_15_1","unstructured":"Edward Jung and Lilian Bossuet . 2017. IP FSM watermarking . In Foundations of Hardware IP Protection . Springer , 65--84. Edward Jung and Lilian Bossuet. 2017. IP FSM watermarking. In Foundations of Hardware IP Protection. Springer, 65--84."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/95.486568"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2013.6581566"},{"key":"e_1_2_1_18_1","first-page":"25","article-title":"Reverse engineering of CMOS integrated circuits","volume":"88","author":"Masalskis G.","year":"2015","unstructured":"G. Masalskis and others. 2015 . Reverse engineering of CMOS integrated circuits . Elektron. Elektrotechn. 88 , 8 (2015), 25 -- 28 . G. Masalskis and others. 2015. Reverse engineering of CMOS integrated circuits. Elektron. Elektrotechn. 88, 8 (2015), 25--28.","journal-title":"Elektron. Elektrotechn."},{"issue":"5","key":"e_1_2_1_19_1","first-page":"422","article-title":"Method of fabricating a tungsten contact. (June 6 1995)","author":"Nicholls Howard C.","year":"1995","unstructured":"Howard C. Nicholls , Michael J. Norrington , and Michael K. Thompson . 1995 . Method of fabricating a tungsten contact. (June 6 1995) . Patent No. 5 , 422 ,308. Howard C. Nicholls, Michael J. Norrington, and Michael K. Thompson. 1995. Method of fabricating a tungsten contact. (June 6 1995). Patent No. 5,422,308.","journal-title":"Patent"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the IEEE Annual Symposium on VLSI. 5--7.","author":"Parham J.","year":"2010","unstructured":"J. Parham , Y. Kim , and others. 2010 . Hiding circuit components using boundary blurring techniques . In Proceedings of the IEEE Annual Symposium on VLSI. 5--7. J. Parham, Y. Kim, and others. 2010. Hiding circuit components using boundary blurring techniques. In Proceedings of the IEEE Annual Symposium on VLSI. 5--7."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630091"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2755563"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516656"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2332154"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/2561828.2561985"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.284"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/731957"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5224968"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2609248.2609250"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951805"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060458"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.346.0858"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/333032.333040"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1177\/875647939000600106"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742069"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2003.12.005"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53140-2_7"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/333032.333040"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3173462","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3173462","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3173462","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:02:45Z","timestamp":1750215765000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3173462"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,30]]},"references-count":40,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2018,4,30]]}},"alternative-id":["10.1145\/3173462"],"URL":"https:\/\/doi.org\/10.1145\/3173462","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2018,4,30]]},"assertion":[{"value":"2017-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-07-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}