{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:51Z","timestamp":1750221291957,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,2,15]],"date-time":"2018-02-15T00:00:00Z","timestamp":1518652800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["IIP-1161022 and EEC-0642422"],"award-info":[{"award-number":["IIP-1161022 and EEC-0642422"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,2,15]]},"DOI":"10.1145\/3174243.3174262","type":"proceedings-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T16:12:59Z","timestamp":1519402379000},"page":"173-182","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems"],"prefix":"10.1145","author":[{"given":"Greg","family":"Stitt","sequence":"first","affiliation":[{"name":"University of Florida, Gainesville, FL, USA"}]},{"given":"Abhay","family":"Gupta","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL, USA"}]},{"given":"Madison N.","family":"Emas","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL, USA"}]},{"given":"David","family":"Wilson","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL, USA"}]},{"given":"Austin","family":"Baylis","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL, USA"}]}],"member":"320","published-online":{"date-parts":[[2018,2,15]]},"reference":[{"volume-title":"Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on. 126--131","author":"Asano S.","key":"e_1_3_2_1_1_1"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2659000"},{"volume-title":"Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on. 111 --118","author":"Cope B.","key":"e_1_3_2_1_3_1"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1764631.1764645"},{"key":"e_1_3_2_1_5_1","unstructured":"Mouser Electronics. 2017. Intel Arria 10 GX 1150 Series FPGA - Field Programmable Gate Array. (September 2017). http: \/\/www.mouser.com\/Intel\/Semiconductors\/Programmable-Logic-ICs\/ FPGA-Field-Programmable-Gate-Array\/Arria-10-GX-1150-Series\/_\/N-3oh9p? P=1ypc7usZ1yy6lwu  Mouser Electronics. 2017. Intel Arria 10 GX 1150 Series FPGA - Field Programmable Gate Array. (September 2017). http: \/\/www.mouser.com\/Intel\/Semiconductors\/Programmable-Logic-ICs\/ FPGA-Field-Programmable-Gate-Array\/Arria-10-GX-1150-Series\/_\/N-3oh9p? P=1ypc7usZ1yy6lwu"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400684"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650344"},{"key":"e_1_3_2_1_8_1","unstructured":"Gidel. 2017. Proc10A PCIe Arria 10 Accelerator Boards. (2017). http:\/\/www.gidel. com\/HPC-RC\/Proc10A_HPC.asp  Gidel. 2017. Proc10A PCIe Arria 10 Accelerator Boards. (2017). http:\/\/www.gidel. com\/HPC-RC\/Proc10A_HPC.asp"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/997163.997199"},{"key":"e_1_3_2_1_10_1","unstructured":"PK Gupta. 2016. Accelerating Datacenter Workloads. (2016). http:\/\/www.fpl2016. org\/slides\/Gupta%20--%20Accelerating%20Datacenter%20Workloads.pdf FPL 2016 Keynote.  PK Gupta. 2016. Accelerating Datacenter Workloads. (2016). http:\/\/www.fpl2016. org\/slides\/Gupta%20--%20Accelerating%20Datacenter%20Workloads.pdf FPL 2016 Keynote."},{"key":"e_1_3_2_1_11_1","volume-title":"Proceedings of the 32Nd International Conference on International Conference on Machine Learning -","volume":"37","author":"Gupta Suyog","year":"2015"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2017.8091072"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.84"},{"volume-title":"Advances in Neural Information Processing Systems 25","author":"Krizhevsky Alex","key":"e_1_3_2_1_14_1"},{"key":"e_1_3_2_1_15_1","unstructured":"Nallatech. 2017. Nallatech 385A FPGA Accelerator Card. (2017). http:\/\/ www.nallatech.com\/store\/fpga-accelerated-computing\/pcie-accelerator-cards\/ nallatech-385a-arria10--1150-fpga\/  Nallatech. 2017. Nallatech 385A FPGA Accelerator Card. (2017). http:\/\/ www.nallatech.com\/store\/fpga-accelerated-computing\/pcie-accelerator-cards\/ nallatech-385a-arria10--1150-fpga\/"},{"key":"e_1_3_2_1_16_1","unstructured":"Nallatech. 2017. Nallatech 510T Compute Acceleration Card. (2017). http:\/\/www.nallatech.com\/store\/fpga-accelerated-computing\/ pcie-accelerator-cards\/nallatech-510t-fpga-computing-acceleration-card\/  Nallatech. 2017. Nallatech 510T Compute Acceleration Card. (2017). http:\/\/www.nallatech.com\/store\/fpga-accelerated-computing\/ pcie-accelerator-cards\/nallatech-510t-fpga-computing-acceleration-card\/"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021740"},{"volume-title":"2016 International Conference on Field-Programmable Technology (FPT). 77--84","author":"Nurvitadhi E.","key":"e_1_3_2_1_18_1"},{"key":"e_1_3_2_1_19_1","unstructured":"Nvidia. 2017. Tesla P100: The Most Advanced Data Center GPU Ever Built. (2017). http:\/\/www.nvidia.com\/object\/tesla-p100.html  Nvidia. 2017. Tesla P100: The Most Advanced Data Center GPU Ever Built. (2017). http:\/\/www.nvidia.com\/object\/tesla-p100.html"},{"volume-title":"2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP). 155--163","author":"Ozkan M. A.","key":"e_1_3_2_1_20_1"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_3_2_1_22_1","unstructured":"Baidu Research. 2017. DeepBench. (2017). https:\/\/svail.github.io\/DeepBench\/  Baidu Research. 2017. DeepBench. (2017). https:\/\/svail.github.io\/DeepBench\/"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2800789"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"crossref","unstructured":"Endong Wang Qing Zhang Bo Shen Guangyong Zhang Xiaowei Lu Qing Wu and Yajuan Wang. 2014. Intel Math Kernel Library. Springer International Publishing Cham 167--188.  Endong Wang Qing Zhang Bo Shen Guangyong Zhang Xiaowei Lu Qing Wu and Yajuan Wang. 2014. Intel Math Kernel Library. Springer International Publishing Cham 167--188.","DOI":"10.1007\/978-3-319-06486-4_7"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2012.39"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.29"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021727"}],"event":{"name":"FPGA '18: The 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey CALIFORNIA USA","acronym":"FPGA '18"},"container-title":["Proceedings of the 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174262","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3174243.3174262","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3174243.3174262","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:33Z","timestamp":1750212693000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174262"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,15]]},"references-count":27,"alternative-id":["10.1145\/3174243.3174262","10.1145\/3174243"],"URL":"https:\/\/doi.org\/10.1145\/3174243.3174262","relation":{},"subject":[],"published":{"date-parts":[[2018,2,15]]},"assertion":[{"value":"2018-02-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}