{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:34:36Z","timestamp":1773246876568,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,2,15]],"date-time":"2018-02-15T00:00:00Z","timestamp":1518652800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,2,15]]},"DOI":"10.1145\/3174243.3174264","type":"proceedings-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T16:12:59Z","timestamp":1519402379000},"page":"127-136","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":115,"title":["Dynamically Scheduled High-level Synthesis"],"prefix":"10.1145","author":[{"given":"Lana","family":"Josipovi\u0107","sequence":"first","affiliation":[{"name":"\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"Radhika","family":"Ghosal","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechniquecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2018,2,15]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488796"},{"key":"e_1_3_2_1_2_1","unstructured":"Amazon.com Inc. Amazon EC2 F1 Instances.  Amazon.com Inc. Amazon EC2 F1 Instances."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430572"},{"key":"e_1_3_2_1_4_1","volume-title":"Pegasus: An efficient intermediate representation","author":"Budiu M.","year":"2002","unstructured":"M. Budiu and S. C. Goldstein . Pegasus: An efficient intermediate representation . Technical Report Carnegie Mellon University-CS-02--107, Carnegie Mellon University , May 2002 . M. Budiu and S. C. Goldstein. Pegasus: An efficient intermediate representation. Technical Report Carnegie Mellon University-CS-02--107, Carnegie Mellon University, May 2002."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/2362088.2362090"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783710"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2205998"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967077"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2857658"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147077"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2456189"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52417"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593143"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021754"},{"key":"e_1_3_2_1_16_1","volume-title":"Synthesis and Optimization of Digital Circuits","author":"Micheli G. De","year":"1994","unstructured":"G. De Micheli . Synthesis and Optimization of Digital Circuits . McGraw-Hill , New York , 1994 . G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, 1994."},{"key":"e_1_3_2_1_17_1","unstructured":"J. C. Dvorak. How the Itanium Killed the Computer Industry Jan. 2009.  J. C. Dvorak. How the Itanium Killed the Computer Industry Jan. 2009."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/45.1.12"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3127041.3127055"},{"key":"e_1_3_2_1_20_1","volume-title":"High-Level Synthesis Blue Book","author":"Fingeroff M.","year":"2010","unstructured":"M. Fingeroff . High-Level Synthesis Blue Book . Xlibris Corporation , first edition, 2010 . M. Fingeroff. High-Level Synthesis Blue Book. Xlibris Corporation, first edition, 2010."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629989"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927454"},{"key":"e_1_3_2_1_23_1","volume-title":"Computer Architecture: A Quantitative Approach. Morgan Kaufmann","author":"Hennessy J. L.","year":"2011","unstructured":"J. L. Hennessy and D. A. Patterson . Computer Architecture: A Quantitative Approach. Morgan Kaufmann , fifth edition, 2011 . J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, fifth edition, 2011."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403449"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435296"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126525"},{"key":"e_1_3_2_1_27_1","first-page":"434","volume-title":"Proceedings of the 27th International Conference on Computer-Aided Design","author":"Kam T.","year":"2008","unstructured":"T. Kam , M. Kishinevsky , J. Cortadella , and M. Galceran-Oms . Correct-byconstruction microarchitectural pipelining . Proceedings of the 27th International Conference on Computer-Aided Design , pages 434 -- 441 , Nov. 2008 . T. Kam, M. Kishinevsky, J. Cortadella, and M. Galceran-Oms. Correct-byconstruction microarchitectural pipelining. Proceedings of the 27th International Conference on Computer-Aided Design, pages 434--41, Nov. 2008."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.31"},{"key":"e_1_3_2_1_30_1","unstructured":"The LLVM Compiler Infrastructure. http:\/\/www.llvm.org.  The LLVM Compiler Infrastructure. http:\/\/www.llvm.org."},{"key":"e_1_3_2_1_31_1","unstructured":"Mentor Graphics. ModelSim 2016.  Mentor Graphics. ModelSim 2016."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.24143"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.10"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2088950"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344720"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF03356742"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2009.5411011"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840831"},{"key":"e_1_3_2_1_40_1","volume-title":"Engineering a Compiler. Morgan Kaufmann","author":"Torczon L.","year":"2011","unstructured":"L. Torczon and K. Cooper . Engineering a Compiler. Morgan Kaufmann , second edition, 2011 . L. Torczon and K. Cooper. Engineering a Compiler. Morgan Kaufmann, second edition, 2011."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3033019.3033027"},{"key":"e_1_3_2_1_42_1","first-page":"171","volume-title":"Proceedings of the 9th International Conference on Formal Methods and Models for Codesign","author":"Vijayaraghavan M.","year":"2009","unstructured":"M. Vijayaraghavan and Arvind. Bounded dataflow networks and latencyinsensitive circuits . In Proceedings of the 9th International Conference on Formal Methods and Models for Codesign , pages 171 -- 180 , Cambridge, MA , July 2009 . M. Vijayaraghavan and Arvind. Bounded dataflow networks and latencyinsensitive circuits. In Proceedings of the 9th International Conference on Formal Methods and Models for Codesign, pages 171--80, Cambridge, MA, July 2009."},{"key":"e_1_3_2_1_43_1","unstructured":"Xilinx Inc. Vivado High-Level Synthesis.  Xilinx Inc. Vivado High-Level Synthesis."}],"event":{"name":"FPGA '18: The 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Monterey CALIFORNIA USA","acronym":"FPGA '18","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174264","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3174243.3174264","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:33Z","timestamp":1750212693000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174264"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,15]]},"references-count":43,"alternative-id":["10.1145\/3174243.3174264","10.1145\/3174243"],"URL":"https:\/\/doi.org\/10.1145\/3174243.3174264","relation":{},"subject":[],"published":{"date-parts":[[2018,2,15]]},"assertion":[{"value":"2018-02-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}