{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,7]],"date-time":"2026-05-07T16:23:48Z","timestamp":1778171028544,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,2,15]],"date-time":"2018-02-15T00:00:00Z","timestamp":1518652800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Intel Hardware Accelerator Research Program"},{"name":"US National Science Foundation","award":["CNS-1643351, ACI-1339756 and CCF-1320211"],"award-info":[{"award-number":["CNS-1643351, ACI-1339756 and CCF-1320211"]}]},{"name":"Intel Strategic Research Alliance"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,2,15]]},"DOI":"10.1145\/3174243.3174265","type":"proceedings-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T16:12:59Z","timestamp":1519402379000},"page":"117-126","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":74,"title":["A Framework for Generating High Throughput CNN Implementations on FPGAs"],"prefix":"10.1145","author":[{"given":"Hanqing","family":"Zeng","sequence":"first","affiliation":[{"name":"University of Southern California, Los Angeles, CA, USA"}]},{"given":"Ren","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Southern California, Los Angeles, CA, USA"}]},{"given":"Chi","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Southern California, Los Angeles, CA, USA"}]},{"given":"Viktor","family":"Prasanna","sequence":"additional","affiliation":[{"name":"University of Southern California, Los Angeles, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2018,2,15]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2015. Intel Inc. Xeon+FPGA Platform for the Data Center. (2015). https:\/\/www. ece.cmu.edu\/calcm\/carl\/lib\/exe\/fetch.php?media=carl15-gupta.pdf  2015. Intel Inc. Xeon+FPGA Platform for the Data Center. (2015). https:\/\/www. ece.cmu.edu\/calcm\/carl\/lib\/exe\/fetch.php?media=carl15-gupta.pdf"},{"key":"e_1_3_2_1_2_1","volume-title":"2013 23rd Intl. Conf. on Field programmable Logic and Applications.","author":"Chen R."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Y. H. Chen J. Emer and V. Sze. 2017. Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37 3 (2017).  Y. H. Chen J. Emer and V. Sze. 2017. Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37 3 (2017).","DOI":"10.1109\/MM.2017.54"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2010.2044260"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:19840012"},{"key":"e_1_3_2_1_7_1","volume-title":"2016 26th International Conference on Field Programmable Logic and Applications (FPL)","author":"Li Huimin","year":"2016"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"e_1_3_2_1_9_1","volume-title":"NIPS'12","author":"Krizhevsky Alex"},{"key":"e_1_3_2_1_10_1","unstructured":"Andrew Lavin. 2015. Fast Algorithms for Convolutional Neural Networks. CoRR abs\/1509.09308 (2015).  Andrew Lavin. 2015. Fast Algorithms for Convolutional Neural Networks. CoRR abs\/1509.09308 (2015)."},{"key":"e_1_3_2_1_11_1","unstructured":"Jonathan Long Evan Shelhamer and Trevor Darrell. 2014. Fully Convolutional Networks for Semantic Segmentation. CoRR abs\/1411.4038 (2014).  Jonathan Long Evan Shelhamer and Trevor Darrell. 2014. Fully Convolutional Networks for Semantic Segmentation. CoRR abs\/1411.4038 (2014)."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2004.840306"},{"key":"e_1_3_2_1_14_1","volume-title":"2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).","author":"Podili A."},{"key":"e_1_3_2_1_15_1","unstructured":"Karen Simonyan and Andrew Zisserman. 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. CoRR abs\/1409.1556 (2014).  Karen Simonyan and Andrew Zisserman. 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. CoRR abs\/1409.1556 (2014)."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"Christian Szegedy Wei Liu Yangqing Jia Pierre Sermanet Scott E. Reed Dragomir Anguelov Dumitru Erhan Vincent Vanhoucke and Andrew Rabinovich. 2014. Going Deeper with Convolutions. CoRR abs\/1409.4842 (2014).  Christian Szegedy Wei Liu Yangqing Jia Pierre Sermanet Scott E. Reed Dragomir Anguelov Dumitru Erhan Vincent Vanhoucke and Andrew Rabinovich. 2014. Going Deeper with Convolutions. CoRR abs\/1409.4842 (2014).","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"e_1_3_2_1_17_1","unstructured":"Xianyi Zhang etal 2017. OpenBLAS. (2017). \"www.openblas.net\"  Xianyi Zhang et al. 2017. OpenBLAS. (2017). \"www.openblas.net\""},{"key":"e_1_3_2_1_18_1","volume-title":"2016 26th International Conference on Field Programmable Logic and Applications (FPL).","author":"Ma Yufei","year":"2016"},{"key":"e_1_3_2_1_19_1","unstructured":"Hanqing Zeng Ren Chen and Viktor K. Prasanna. 2017. Optimizing Frequency Domain Implementation of CNNs on FPGAs. Technical Report. University of Southern California. http:\/\/ceng.usc.edu\/techreports\/2017\/Prasanna%20CENG-2017--3.pdf  Hanqing Zeng Ren Chen and Viktor K. Prasanna. 2017. Optimizing Frequency Domain Implementation of CNNs on FPGAs. Technical Report. University of Southern California. http:\/\/ceng.usc.edu\/techreports\/2017\/Prasanna%20CENG-2017--3.pdf"},{"key":"e_1_3_2_1_20_1","volume-title":"Fast Generation of High Throughput Customized Deep Learning Accelerators on FPGAs. In 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).","author":"Zeng Hanqing","year":"2017"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021727"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021698"}],"event":{"name":"FPGA '18: The 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Monterey CALIFORNIA USA","acronym":"FPGA '18","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174265","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3174243.3174265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:33Z","timestamp":1750212693000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174265"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,15]]},"references-count":22,"alternative-id":["10.1145\/3174243.3174265","10.1145\/3174243"],"URL":"https:\/\/doi.org\/10.1145\/3174243.3174265","relation":{},"subject":[],"published":{"date-parts":[[2018,2,15]]},"assertion":[{"value":"2018-02-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}