{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T09:04:00Z","timestamp":1768986240410,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,2,15]],"date-time":"2018-02-15T00:00:00Z","timestamp":1518652800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,2,15]]},"DOI":"10.1145\/3174243.3174273","type":"proceedings-article","created":{"date-parts":[[2018,2,23]],"date-time":"2018-02-23T16:12:59Z","timestamp":1519402379000},"page":"183-188","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["High-Performance QR Decomposition for FPGAs"],"prefix":"10.1145","author":[{"given":"Martin","family":"Langhammer","sequence":"first","affiliation":[{"name":"Intel, High Wycombe, United Kingdom"}]},{"given":"Bogdan","family":"Pasca","sequence":"additional","affiliation":[{"name":"Intel, Toulouse, France"}]}],"member":"320","published-online":{"date-parts":[[2018,2,15]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2012. LogiCORE IP CORDIC v6.0. https:\/\/www.xilinx.com\/support\/ documentation\/ip_documentation\/floating_point\/v6_0\/ds816_floating_point. pdf.  2012. LogiCORE IP CORDIC v6.0. https:\/\/www.xilinx.com\/support\/ documentation\/ip_documentation\/floating_point\/v6_0\/ds816_floating_point. pdf."},{"key":"e_1_3_2_1_2_1","unstructured":"2017. DSP Builder Advanced Blockset. (2017). https:\/\/www.altera.com\/products\/ design-software\/model--simulation\/dsp-builder\/overview.html.  2017. DSP Builder Advanced Blockset. (2017). https:\/\/www.altera.com\/products\/ design-software\/model--simulation\/dsp-builder\/overview.html."},{"key":"e_1_3_2_1_3_1","volume-title":"2016 5th International Conference on Electronic Devices, Systems and Applications (ICEDSA). 1--4.","author":"Alhamed A."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2047744"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2133173.2133179"},{"key":"e_1_3_2_1_6_1","volume-title":"FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm. In Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers","author":"Karkooti M.","year":"2005"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1513895.1513904"},{"key":"e_1_3_2_1_8_1","volume-title":"QRD for Parallel Arithmetic Structures. In 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH). 146--147","author":"Langhammer M.","year":"2017"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2015.0349"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"V. Mauer and M. Parker. 2011. Floating point STAP implementation on FPGAs. In 2011 IEEE RadarCon (RADAR). 901--904.  V. Mauer and M. Parker. 2011. Floating point STAP implementation on FPGAs. In 2011 IEEE RadarCon (RADAR). 901--904.","DOI":"10.1109\/RADAR.2011.5960667"},{"key":"e_1_3_2_1_11_1","unstructured":"Luke Miller. 2014. Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA. Xilinx Whitepaper (June 2014). https:\/\/www.xilinx.com\/support\/ documentation\/white_papers\/wp452-adaptive-beamforming.pdf.  Luke Miller. 2014. Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA. Xilinx Whitepaper (June 2014). https:\/\/www.xilinx.com\/support\/ documentation\/white_papers\/wp452-adaptive-beamforming.pdf."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435753"},{"key":"e_1_3_2_1_13_1","volume-title":"2016 IEEE National Aerospace and Electronics Conference (NAECON) and Ohio Innovation Summit (OIS). 416--421","author":"Parker M."},{"key":"e_1_3_2_1_14_1","unstructured":"Jimmy Pettersson and Ian Wainwright. 2010. Radar Signal Processing with Graphics Processors (GPUs). In SAAB.  Jimmy Pettersson and Ian Wainwright. 2010. Radar Signal Processing with Graphics Processors (GPUs). In SAAB."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596532.1596535"}],"event":{"name":"FPGA '18: The 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Monterey CALIFORNIA USA","acronym":"FPGA '18","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174273","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3174243.3174273","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:33Z","timestamp":1750212693000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3174243.3174273"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2,15]]},"references-count":15,"alternative-id":["10.1145\/3174243.3174273","10.1145\/3174243"],"URL":"https:\/\/doi.org\/10.1145\/3174243.3174273","relation":{},"subject":[],"published":{"date-parts":[[2018,2,15]]},"assertion":[{"value":"2018-02-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}