{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:07:13Z","timestamp":1750306033651,"version":"3.41.0"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2018,1,4]],"date-time":"2018-01-04T00:00:00Z","timestamp":1515024000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGBED Rev."],"published-print":{"date-parts":[[2018,1,4]]},"abstract":"<jats:p>Mixed-critical platforms require an on-chip interconnect and a memory controller capable of providing sufficient timing independence for critical applications. Existing real-time memory controllers, however, either do not support mixed criticality or still fail to ensure negligible allow a certain degree of interference between applications.<\/jats:p>\n          <jats:p>On the other hand, Networks-on-Chip manage the traffic injection rate mainly by employing complex techniques; either back-pressure based flow-control mechanisms or rate-control of traffic load (i.e. traffic shaping). This work proposes such a Traffic Shaper Module that supports both monitoring and traffic control at the on-chip network interface or the memory controller.<\/jats:p>\n          <jats:p>The advantage of this Traffic Shaper Module is that at system level it provides guaranteed memory bandwidth to the critical applications by limiting traffic of non-critical tasks.<\/jats:p>\n          <jats:p>The system is developed in the Xilinx ZYNQ7000 System-on-Chip while the measurements were captured on a Zed-board development board. By enabling the Traffic Shaper in our architecture we achieved fine-grain bandwidth control with negligible overhead, while providing bandwidth of only 0.5-5 percent less than the theoretical specified bandwidth.<\/jats:p>","DOI":"10.1145\/3177803.3177807","type":"journal-article","created":{"date-parts":[[2018,1,4]],"date-time":"2018-01-04T16:27:31Z","timestamp":1515083251000},"page":"21-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Towards architectural support for bandwidth management in mixed-critical embedded systems"],"prefix":"10.1145","volume":"14","author":[{"given":"Ioannis","family":"Christoforakis","sequence":"first","affiliation":[{"name":"Universita Politecnica Delle Marche of Ancona"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maria","family":"Astrinaki","sequence":"additional","affiliation":[{"name":"Technological Institute of Crete, Heraklion, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Kornaros","sequence":"additional","affiliation":[{"name":"Technological Institute of Crete, Heraklion, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,1,4]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"243","volume-title":"Symp., (RTSS)","author":"Vestal S.","year":"2007","unstructured":"S. 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