{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,7]],"date-time":"2026-07-07T08:56:06Z","timestamp":1783414566202,"version":"3.54.6"},"reference-count":94,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2018,3,22]],"date-time":"2018-03-22T00:00:00Z","timestamp":1521676800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100007000","name":"Laboratory-Directed Research and Development (LDRD) Project","doi-asserted-by":"crossref","award":["180819"],"award-info":[{"award-number":["180819"]}],"id":[{"id":"10.13039\/100007000","id-type":"DOI","asserted-by":"crossref"}]},{"name":"National Technology and Engineering Solutions of Sandia, LLC."},{"name":"Honeywell International, Inc."},{"name":"U.S. Department of Energy's National Nuclear Security Administration","award":["DE-NA0003525"],"award-info":[{"award-number":["DE-NA0003525"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2018,3,31]]},"abstract":"<jats:p>\n            Dennard scaling has ended. Lowering the voltage supply (\n            <jats:italic>V<\/jats:italic>\n            <jats:sub>\n              <jats:italic>dd<\/jats:italic>\n            <\/jats:sub>\n            ) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower\n            <jats:italic>V<\/jats:italic>\n            <jats:sub>\n              <jats:italic>dd<\/jats:italic>\n            <\/jats:sub>\n            in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower\n            <jats:italic>V<\/jats:italic>\n            <jats:sub>\n              <jats:italic>dd<\/jats:italic>\n            <\/jats:sub>\n            . One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. From the simulation results, this RRNS system can reduce the energy-delay-product by about 3\u00d7 for multiplication intensive workloads and by about 2\u00d7 in general, when compared to a non-error-correcting binary core.\n          <\/jats:p>","DOI":"10.1145\/3177837","type":"journal-article","created":{"date-parts":[[2018,3,23]],"date-time":"2018-03-23T12:29:49Z","timestamp":1521808189000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Extending Moore\u2019s Law via Computationally Error-Tolerant Computing"],"prefix":"10.1145","volume":"15","author":[{"given":"Bobin","family":"Deng","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sriseshan","family":"Srikanth","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eric R.","family":"Hein","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thomas M.","family":"Conte","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Erik","family":"Debenedictis","sequence":"additional","affiliation":[{"name":"Sandia National Laboratories, Albuquerque, NM"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeanine","family":"Cook","sequence":"additional","affiliation":[{"name":"Sandia National Laboratories, Albuquerque, NM"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael P.","family":"Frank","sequence":"additional","affiliation":[{"name":"Sandia National Laboratories, Albuquerque, NM"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,3,22]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Daniel Anderson. 2014. Design and implementation of an instruction set architecture and an instruction execution unit for the REZ9 coprocessor system. M.S. thesis University of Nevada Las Vegas (2014).  Daniel Anderson. 2014. Design and implementation of an instruction set architecture and an instruction execution unit for the REZ9 coprocessor system. M.S. thesis University of Nevada Las Vegas (2014)."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320111"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2016.16"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.2"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.224055"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219855"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/81.678485"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2015.2484118"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/0898-1221(91)90200-N"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629395.1629401"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the IEEE International Conference on Rebooting Computing (ICRC\u201916)","author":"Deng B."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.214689"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.381948"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-013-5421-9"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956571"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1980.1163442"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04468-7_23"},{"key":"e_1_2_1_19_1","volume-title":"IFAC\/IFIP\/IFORS Symposium. 79--84","author":"Forin P.","year":"1989"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403462"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2008.050401"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/301250.301309"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658654"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1899390.1899394"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the Region Six Annual Conference. IEEE, 429--464","author":"Hastings C. W.","year":"1966"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, 247--256","author":"Hsu Yuang-Ming"},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE, 247--256","author":"Hsu Yuang-Ming"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(94)00099-9"},{"key":"e_1_2_1_29_1","unstructured":"IBM. 2014. IBM power system E880 server an IBM POWER8 technology-based system addresses the requirements of an industry-leading enterprise class system. IBM Europe Middle East and Africa Hardware Announcement ZG14-0262.  IBM. 2014. IBM power system E880 server an IBM POWER8 technology-based system addresses the requirements of an industry-leading enterprise class system. IBM Europe Middle East and Africa Hardware Announcement ZG14-0262."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.281"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.281"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.481482"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.34"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2501319"},{"key":"e_1_2_1_35_1","volume-title":"CMOS and Beyond: Logic Switches for Terascale Integrated Circuits","author":"Khan Asif Islam"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131532"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11018-008-9042-0"},{"key":"e_1_2_1_38_1","unstructured":"Hari Krishna Bal Krishna Kuo-Yu Lin and Jenn-Dong Sun. 1994. Computational Number Theory and Digital Signal Processing: Fast Algorithms and Error Control Techniques. Vol. 6. CRC Press.   Hari Krishna Bal Krishna Kuo-Yu Lin and Jenn-Dong Sun. 1994. Computational Number Theory and Digital Signal Processing: Fast Algorithms and Error Control Techniques. Vol. 6. CRC Press."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.204106"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2011.18"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.4236\/wet.2013.44029"},{"key":"e_1_2_1_43_1","unstructured":"Florence Jessie MacWilliams and Neil James Alexander Sloane. 1977. The Theory of Error-correcting Codes. Elsevier.  Florence Jessie MacWilliams and Neil James Alexander Sloane. 1977. The Theory of Error-correcting Codes. Elsevier."},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.80"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2010.28"},{"key":"e_1_2_1_46_1","unstructured":"A. McMenamin. 2013. The end of dennard scaling.  A. McMenamin. 2013. The end of dennard scaling."},{"key":"e_1_2_1_47_1","volume-title":"Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD\u201907)","author":"Mizan Elias"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.800526"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1994.326816"},{"key":"e_1_2_1_50_1","volume-title":"Proceedings of the European Design, Automation and Test Conference. IEEE, 7--14","author":"Nicolaidis Michael"},{"key":"e_1_2_1_51_1","unstructured":"Eric B. Olsen. 2015. Introduction of the residue number arithmetic logic unit with brief computational complexity analysis (Rez-9 soft processor). Whitepaper Digital System Research (2015).  Eric B. Olsen. 2015. Introduction of the residue number arithmetic logic unit with brief computational complexity analysis (Rez-9 soft processor). Whitepaper Digital System Research (2015)."},{"key":"e_1_2_1_52_1","unstructured":"Amos Omondi and Benjamin Premkumar. Residue Number Systems: Theory and Implementation. Imperial College Press.   Amos Omondi and Benjamin Premkumar. Residue Number Systems: Theory and Implementation. Imperial College Press."},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.177315"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676055"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.56"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.56"},{"key":"e_1_2_1_57_1","volume-title":"Proceedings of the 42nd Midwest Symposium on Circuits and Systems","volume":"1","author":"Preethy A. P."},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20000529"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676264"},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20020192"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1970.222937"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403461"},{"key":"e_1_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2006.23"},{"key":"e_1_2_1_64_1","unstructured":"Stefan Rusu. 2010. Multi-domain processors design overview. ISCA Tutorial on Multi-domain Processors: Challenges Design Methods and Recent Developments (June 2010). Saint Malo France.  Stefan Rusu. 2010. Multi-domain processors design overview. ISCA Tutorial on Multi-domain Processors: Challenges Design Methods and Recent Developments (June 2010). Saint Malo France."},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796789"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.5555\/1886301.1886318"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/TWC.2013.031813.121113"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822775"},{"key":"e_1_2_1_69_1","unstructured":"Sriseshan Srikanth Bobin Deng and Thomas M. Conte. 2016. A brief survey of non-residue based computational error correction. arXiv Preprint arXiv:1611.03099 (2016).  Sriseshan Srikanth Bobin Deng and Thomas M. Conte. 2016. A brief survey of non-residue based computational error correction. arXiv Preprint arXiv:1611.03099 (2016)."},{"key":"e_1_2_1_70_1","unstructured":"S. Srikanth P. G. Rabbat E. R. Hein B. Deng T. M. Conte E. DeBenedictis J. Cook and M Frank. Memory system design for ultra low power computationally error resilient processor microarchitectures (unpublished).  S. Srikanth P. G. Rabbat E. R. Hein B. Deng T. M. Conte E. DeBenedictis J. Cook and M Frank. Memory system design for ultra low power computationally error resilient processor microarchitectures (unpublished)."},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.57044"},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.204107"},{"key":"e_1_2_1_73_1","volume-title":"Proceedings of the 1992 IEEE International Symposium on Circuits and Systems (ISCAS\u201992)","volume":"2","author":"Sun J.-D."},{"key":"e_1_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2010.5510255"},{"key":"e_1_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011442703770"},{"key":"e_1_2_1_76_1","unstructured":"Nicholas S. Szabo and Richard I. Tanaka. 1967. Residue Arithmetic and its Applications to Computer Technology. McGraw--Hill.  Nicholas S. Szabo and Richard I. Tanaka. 1967. Residue Arithmetic and its Applications to Computer Technology. McGraw--Hill."},{"key":"e_1_2_1_77_1","first-page":"156","article-title":"Process for determining competing cause event probability and\/or system availability during the simultaneous occurrence of multiple events. (Apr. 22, 2004)","volume":"10","author":"Tan J.","year":"2004","journal-title":"US Patent App."},{"key":"e_1_2_1_78_1","volume-title":"Proceedings of the 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP\u201910)","author":"Tang Yangyang","year":"2010"},{"key":"e_1_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865493"},{"key":"e_1_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2435773"},{"key":"e_1_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1149\/1.3700933"},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2066531"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.5555\/1302493.1302736"},{"key":"e_1_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.15"},{"key":"e_1_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.910537"},{"key":"e_1_2_1_86_1","volume-title":"Automata Studies","author":"Neumann John Von"},{"key":"e_1_2_1_87_1","volume-title":"Proceedings of SPIE\u2019s 48th Annual Meeting on Optical Science and Technology. International Society for Optics and Photonics, 573--584","author":"Arnold E. George Walters III"},{"key":"e_1_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/INDIN.2007.4384907"},{"key":"e_1_2_1_89_1","unstructured":"R. W. Watson. 1965. Error detection and correction and other residue interacting operations in a residue redundant number system. University of California Berkeley.  R. W. Watson. 1965. Error detection and correction and other residue interacting operations in a residue redundant number system. University of California Berkeley."},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1966.5275"},{"key":"e_1_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.16.0115.0575"},{"key":"e_1_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2015.2400997"},{"key":"e_1_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223594"},{"key":"e_1_2_1_94_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1190587"},{"key":"e_1_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCAS.2013.6765313"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3177837","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3177837","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:02:54Z","timestamp":1750215774000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3177837"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3,22]]},"references-count":94,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2018,3,31]]}},"alternative-id":["10.1145\/3177837"],"URL":"https:\/\/doi.org\/10.1145\/3177837","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3,22]]},"assertion":[{"value":"2017-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-03-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}