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Storage"],"published-print":{"date-parts":[[2018,2,28]]},"abstract":"<jats:p>\n            Emerging non-volatile memory (NVM) offers non-volatility, byte-addressability, and fast access at the same time. It is suggested that programs should access NVM directly through CPU load and store instructions. To guarantee crash consistency, durable transactions are regarded as a common choice of applications for accessing persistent memory data. However, existing durable transaction systems employ either\n            <jats:italic>undo logging<\/jats:italic>\n            , which requires a fence for every memory write, or\n            <jats:italic>redo logging<\/jats:italic>\n            , which requires intercepting all memory reads within transactions. Both approaches incur significant overhead.\n          <\/jats:p>\n          <jats:p>\n            This article presents D\n            <jats:sc>ude<\/jats:sc>\n            T\n            <jats:sc>x<\/jats:sc>\n            , a crash-consistent durable transaction system that avoids the drawbacks of both undo and redo logging. D\n            <jats:sc>ude<\/jats:sc>\n            T\n            <jats:sc>x<\/jats:sc>\n            uses shadow DRAM to\n            <jats:italic>decouple<\/jats:italic>\n            the execution of a durable transaction into three fully asynchronous steps. The advantage is that only minimal fences and no memory read instrumentation are required. This design enables an out-of-the-box concurrency control mechanism, transactional memory or fine-grained locks, to be used as an independent component. The evaluation results show that D\n            <jats:sc>ude<\/jats:sc>\n            T\n            <jats:sc>x<\/jats:sc>\n            adds durability to a software transactional memory system with only 7.4%--24.6% throughput degradation. Compared to typical existing durable transaction systems, D\n            <jats:sc>ude<\/jats:sc>\n            T\n            <jats:sc>x<\/jats:sc>\n            provides 1.7\u00d7 --4.4\u00d7 higher throughput. Moreover, D\n            <jats:sc>ude<\/jats:sc>\n            T\n            <jats:sc>x<\/jats:sc>\n            can be implemented with hardware transactional memory or lock-based concurrency control, leading to a further 1.7\u00d7 and 3.3\u00d7 speedup, respectively.\n          <\/jats:p>","DOI":"10.1145\/3177920","type":"journal-article","created":{"date-parts":[[2018,4,5]],"date-time":"2018-04-05T15:09:51Z","timestamp":1522940991000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["D\n            <scp>ude<\/scp>\n            T\n            <scp>x<\/scp>"],"prefix":"10.1145","volume":"14","author":[{"given":"Mengxing","family":"Liu","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Mingxing","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Kang","family":"Chen","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Xuehai","family":"Qian","sequence":"additional","affiliation":[{"name":"University of Southern California"}]},{"given":"Yongwei","family":"Wu","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Weimin","family":"Zheng","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Jinglei","family":"Ren","sequence":"additional","affiliation":[{"name":"Microsoft Research, Asia"}]}],"member":"320","published-online":{"date-parts":[[2018,4,4]]},"reference":[{"volume-title":"Proc. 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