{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T18:52:22Z","timestamp":1768071142950,"version":"3.49.0"},"reference-count":27,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2018,4,30]],"date-time":"2018-04-30T00:00:00Z","timestamp":1525046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2018,4,30]]},"abstract":"<jats:p>\n            Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width\n            <jats:italic>N<\/jats:italic>\n            of the operands, i.e.,\n            <jats:italic>O<\/jats:italic>\n            (\n            <jats:italic>log<\/jats:italic>\n            <jats:sub>2<\/jats:sub>\n            <jats:italic>N<\/jats:italic>\n            ), and the device count is 5\n            <jats:italic>N<\/jats:italic>\n            . We verify the correctness of the proposed scheme by means of TaO\n            <jats:sub>\u00d7<\/jats:sub>\n            device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices.\n          <\/jats:p>","DOI":"10.1145\/3183352","type":"journal-article","created":{"date-parts":[[2018,7,12]],"date-time":"2018-07-12T15:38:47Z","timestamp":1531409927000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays"],"prefix":"10.1145","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6561-8934","authenticated-orcid":false,"given":"Debjyoti","family":"Bhattacharjee","sequence":"first","affiliation":[{"name":"Nanyang Technological University, Nanyang Avenue, Singapore"}]},{"given":"Anne","family":"Siemon","sequence":"additional","affiliation":[{"name":"RWTH Aachen University, Germany"}]},{"given":"Eike","family":"Linn","sequence":"additional","affiliation":[{"name":"RWTH Aachen University, Germany"}]},{"given":"Stephan","family":"Menzel","sequence":"additional","affiliation":[{"name":"Forschungszentrum J\u00fclich, J\u00fclich, Germany"}]},{"given":"Anupam","family":"Chattopadhyay","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Nanyang Avenue, Singapore"}]}],"member":"320","published-online":{"date-parts":[[2018,7,12]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Memristive","author":"Borghetti Julien","year":"2010","unstructured":"Julien Borghetti , Gregory S. Snider , Philip J. Kuekes , J. Joshua Yang , Duncan R. Stewart , and R. Stanley Williams . 2010. \u201c Memristive \u201d switches enable \u201cstateful\u201d logic operations via material implication. Nature 464, 7290 ( 2010 ), 873--876. Julien Borghetti, Gregory S. Snider, Philip J. Kuekes, J. Joshua Yang, Duncan R. Stewart, and R. Stanley Williams. 2010. \u201cMemristive\u201d switches enable \u201cstateful\u201d logic operations via material implication. Nature 464, 7290 (2010), 873--876."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1002\/adma.200900375"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the 33rd European Solid State Circuits Conference (ESSCIRC\u201907)","author":"Flocke Alexander","unstructured":"Alexander Flocke and Tobias G. Noll . 2007. Fundamental analysis of resistive nano-crossbars for the use in hybrid nano\/CMOS-memory . In Proceedings of the 33rd European Solid State Circuits Conference (ESSCIRC\u201907) . IEEE, 328--331. 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In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS\u201914). IEEE, 1420--1423."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2016.2542879"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916)","author":"Ni Leibin","year":"2016","unstructured":"Leibin Ni , Yuhao Wang , H. Yu , Wei Yang , Chuliang Weng , and Junfeng Zhao . 2016 . An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar . In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916) . 280--285. Leibin Ni, Yuhao Wang, H. Yu, Wei Yang, Chuliang Weng, and Junfeng Zhao. 2016. An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916). 280--285."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2017.10"},{"key":"e_1_2_1_17_1","volume-title":"Realization of minimum and maximum gate function in Ta<sub>2<\/sub>O<sub>5<\/sub>-based memristive devices. Sci. Rep. 6","author":"Breuer Thomas","year":"2016","unstructured":"Thomas Breuer , Lutz Nielen , Bernd Roesgen , Rainer Waser , Vikas Rana , and Eike Linn . 2016. Realization of minimum and maximum gate function in Ta<sub>2<\/sub>O<sub>5<\/sub>-based memristive devices. Sci. Rep. 6 ( 2016 ). Thomas Breuer, Lutz Nielen, Bernd Roesgen, Rainer Waser, Vikas Rana, and Eike Linn. 2016. Realization of minimum and maximum gate function in Ta<sub>2<\/sub>O<sub>5<\/sub>-based memristive devices. Sci. Rep. 6 (2016)."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226356"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers. 162--166","author":"Revanna N.","unstructured":"N. Revanna and E. E. Swartzlander . 2016. Memristor based adder circuit design . In Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers. 162--166 . N. Revanna and E. E. Swartzlander. 2016. Memristor based adder circuit design. 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Morgan Kaufmann . Jose Duato, Sudhakar Yalamanchili, and Lionel M. Ni. 2003. Interconnection Networks: An Engineering Approach. Morgan Kaufmann."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1002\/adfm.201500865"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the 13th International Workshop on Cellular Nanoscale Networks and their Applications.","author":"Kim Seonghyun","unstructured":"Seonghyun Kim , Wootae Lee , and Hyunsang Hwang . Selector devices for cross-point ReRAM . In Proceedings of the 13th International Workshop on Cellular Nanoscale Networks and their Applications. Seonghyun Kim, Wootae Lee, and Hyunsang Hwang. Selector devices for cross-point ReRAM. In Proceedings of the 13th International Workshop on Cellular Nanoscale Networks and their Applications."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1021\/nn3028776"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3183352","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3183352","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:39:13Z","timestamp":1750210753000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3183352"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,30]]},"references-count":27,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2018,4,30]]}},"alternative-id":["10.1145\/3183352"],"URL":"https:\/\/doi.org\/10.1145\/3183352","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4,30]]},"assertion":[{"value":"2017-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-07-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}