{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:32:33Z","timestamp":1750221153249,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,1,23]],"date-time":"2018-01-23T00:00:00Z","timestamp":1516665600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"CNRS, GdR ISIS","award":["Mordred Project"],"award-info":[{"award-number":["Mordred Project"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,1,23]]},"DOI":"10.1145\/3183767.3183780","type":"proceedings-article","created":{"date-parts":[[2018,3,19]],"date-time":"2018-03-19T12:53:23Z","timestamp":1521464003000},"page":"51-56","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures"],"prefix":"10.1145","author":[{"given":"Hugo","family":"Miomandre","sequence":"first","affiliation":[{"name":"IETR, INSA, UBL Rennes, France"}]},{"given":"Julien","family":"Hasco\u00ebt","sequence":"additional","affiliation":[{"name":"Kalray & IETR, Montbonnot-Saint-Martin, France"}]},{"given":"Karol","family":"Desnos","sequence":"additional","affiliation":[{"name":"IETR, INSA, UBL Rennes, France"}]},{"given":"Kevin J. M.","family":"Martin","sequence":"additional","affiliation":[{"name":"Lab-STICC, UBS, Lorient, France"}]},{"given":"Beno\u00eet Dupont","family":"de Dinechin Kalray","sequence":"additional","affiliation":[{"name":"Montbonnot-Saint-Martin, France"}]},{"given":"Jean-Fran\u00e7ois","family":"Nezan","sequence":"additional","affiliation":[{"name":"IETR, INSA, UBL Rennes, France"}]}],"member":"320","published-online":{"date-parts":[[2018,1,23]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"S. C. Brunet C. Alberti M. Mattavelli and J. W. Janneck. 2013. Design space exploration of high level stream programs on parallel architectures: a focus on the buffer size minimization and optimization problem. In Image and Signal Processing and Analysis (ISPA). IEEE 738--743.  S. C. Brunet C. Alberti M. Mattavelli and J. W. Janneck. 2013. Design space exploration of high level stream programs on parallel architectures: a focus on the buffer size minimization and optimization problem. In Image and Signal Processing and Analysis (ISPA). IEEE 738--743.","DOI":"10.1109\/ISPA.2013.6703835"},{"volume-title":"Automation & Test in Europe Conference & Exhibition. IEEE, 1201--1206","author":"Conti F.","key":"e_1_3_2_1_3_1","unstructured":"F. Conti , D. Palossi , A. Marongiu , D. Rossi , and L. Benini . 2016. Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms. In Design , Automation & Test in Europe Conference & Exhibition. IEEE, 1201--1206 . F. Conti, D. Palossi, A. Marongiu, D. Rossi, and L. Benini. 2016. Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms. In Design, Automation & Test in Europe Conference & Exhibition. IEEE, 1201--1206."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670342"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"K. Desnos M. Pelcat J.-F. Nezan S.S. Bhattacharyya and S. Aridhi. 2013. PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Re-configuration. In Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS). IEEE 41--48.  K. Desnos M. Pelcat J.-F. Nezan S.S. Bhattacharyya and S. Aridhi. 2013. PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Re-configuration. In Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS). IEEE 41--48.","DOI":"10.1109\/SAMOS.2013.6621104"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"W. Ecker W. M\u00fcller and R. D\u00f6mer. 2009. Hardware-dependent Software. Springer.   W. Ecker W. M\u00fcller and R. D\u00f6mer. 2009. Hardware-dependent Software. Springer.","DOI":"10.1007\/978-1-4020-9436-1"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"T. Goubier R. Sirdey S. Louise and V. David. 2011. SigmaC: A Programming Model and Language for Embedded Manycores. In Algorithms and Architectures for Parallel Processing. Springer 385--394.   T. Goubier R. Sirdey S. Louise and V. David. 2011. SigmaC: A Programming Model and Language for Embedded Manycores. In Algorithms and Architectures for Parallel Processing. Springer 385--394.","DOI":"10.1007\/978-3-642-24650-0_33"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3139315.3139318"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"J. Hasco\u00ebt K. Desnos J.-F. Nezan and B. D. de Dinechin. 2017. Hierarchical Dataflow Model for Efficient Programming of Clustered Manycore Processors. In Application-specific Systems Architectures and Processors (ASAP).  J. Hasco\u00ebt K. Desnos J.-F. Nezan and B. D. de Dinechin. 2017. Hierarchical Dataflow Model for Efficient Programming of Clustered Manycore Processors. In Application-specific Systems Architectures and Processors (ASAP).","DOI":"10.1109\/ASAP.2017.7995270"},{"volume-title":"Embedded Design in Education and Research Conference (EDERC). 167--171","author":"Heulot J.","key":"e_1_3_2_1_10_1","unstructured":"J. Heulot , M. Pelcat , K. Desnos , J. F. Nezan , and S. Aridhi . 2014. Spider: A Synchronous Parameterized and Interfaced Dataflow-based RTOS for multicore DSPS . In Embedded Design in Education and Research Conference (EDERC). 167--171 . J. Heulot, M. Pelcat, K. Desnos, J. F. Nezan, and S. Aridhi. 2014. Spider: A Synchronous Parameterized and Interfaced Dataflow-based RTOS for multicore DSPS. In Embedded Design in Education and Research Conference (EDERC). 167--171."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.381846"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Y. Lesparre A. Munier-Kordon and J. M. Delosme. 2016. Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures. In Digital System Design (DSD). Euromicro 146--153.  Y. Lesparre A. Munier-Kordon and J. M. Delosme. 2016. Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures. In Digital System Design (DSD). Euromicro 146--153.","DOI":"10.1109\/DSD.2016.52"},{"key":"e_1_3_2_1_15_1","unstructured":"S. Neuendorffer and E.A. Lee. 2004. Hierarchical reconfiguration of dataflow models. In MEMOCODE.  S. Neuendorffer and E.A. Lee. 2004. Hierarchical reconfiguration of dataflow models. In MEMOCODE."},{"key":"e_1_3_2_1_16_1","volume-title":"Epiphany-V: a 1024 processor 64-bit RISC system-on-chip. arXiv preprint arXiv:1610.01832","author":"Olofsson Andreas","year":"2016","unstructured":"Andreas Olofsson . 2016. Epiphany-V: a 1024 processor 64-bit RISC system-on-chip. arXiv preprint arXiv:1610.01832 ( 2016 ). Andreas Olofsson. 2016. Epiphany-V: a 1024 processor 64-bit RISC system-on-chip. arXiv preprint arXiv:1610.01832 (2016)."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2931028.2931033"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3075564.3075568"}],"event":{"name":"PARMA-DITAM '18: 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms","sponsor":["HiPEAC HiPEAC Network of Excellence"],"location":"Manchester United Kingdom","acronym":"PARMA-DITAM '18"},"container-title":["Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3183767.3183780","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3183767.3183780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:29Z","timestamp":1750208909000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3183767.3183780"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1,23]]},"references-count":17,"alternative-id":["10.1145\/3183767.3183780","10.1145\/3183767"],"URL":"https:\/\/doi.org\/10.1145\/3183767.3183780","relation":{},"subject":[],"published":{"date-parts":[[2018,1,23]]},"assertion":[{"value":"2018-01-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}