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Archit. Code Optim."],"published-print":{"date-parts":[[2018,6,30]]},"abstract":"<jats:p>The paradigm shift from planar (two dimensional (2D)) to vertical (three-dimensional (3D)) models has placed the NAND flash technology on the verge of a design evolution that can handle the demands of next-generation storage applications. However, it also introduces challenges that may obstruct the realization of such 3D NAND flash. Specifically, we observed that the fast threshold drift (fast-drift) in a charge-trap flash-based 3D NAND cell can make it lose a critical fraction of the stored charge relatively soon after programming and generate errors.<\/jats:p>\n          <jats:p>\n            In this work, we first present an elastic read reference (\n            <jats:italic>\n              V\n              <jats:sub>Ref<\/jats:sub>\n            <\/jats:italic>\n            ) scheme (ERR) for reducing such errors in ReveNAND\u2014our fast-drift aware 3D NAND design. To address the inherent limitation of the adaptive\n            <jats:italic>\n              V\n              <jats:sub>Ref<\/jats:sub>\n            <\/jats:italic>\n            , we introduce a new intra-block page organization (hitch-hike) that can enable stronger error correction for the error-prone pages. In addition, we propose a novel reinforcement-learning-based smart data refill scheme (iRefill) to counter the impact of fast-drift with minimum performance and hardware overhead. Finally, we present the first analytic model to characterize fast-drift and evaluate its system-level impact. Our results show that, compared to conventional 3D NAND design, our ReveNAND can reduce fast-drift errors by 87%, on average, and can lower the ECC latency and energy overheads by 13\u00d7 and 10\u00d7, respectively.\n          <\/jats:p>","DOI":"10.1145\/3184744","type":"journal-article","created":{"date-parts":[[2018,5,1]],"date-time":"2018-05-01T12:00:39Z","timestamp":1525176039000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["ReveNAND"],"prefix":"10.1145","volume":"15","author":[{"given":"Mustafa M.","family":"Shihab","sequence":"first","affiliation":[{"name":"University of Texas at Dallas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Zhang","sequence":"additional","affiliation":[{"name":"Yonsei University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Myoungsoo","family":"Jung","sequence":"additional","affiliation":[{"name":"Yonsei University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmut","family":"Kandemir","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056062"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657034"},{"key":"e_1_2_1_3_1","first-page":"140","article-title":"Error analysis and retention aware error management for NAND flash memory","volume":"17","author":"Cai Yu","year":"2013","unstructured":"Yu Cai , Gulay Yalcin , Onur Mutlu , Erich F. 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