{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T08:11:53Z","timestamp":1759133513180,"version":"3.41.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2018,5,1]],"date-time":"2018-05-01T00:00:00Z","timestamp":1525132800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"EU H2020 Research and Innovation Programme: \u201cMANGO\u201d","award":["671668"],"award-info":[{"award-number":["671668"]}]},{"name":"\u201cM2DC\u201d","award":["688201"],"award-info":[{"award-number":["688201"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2018,6,30]]},"abstract":"<jats:p>\n            The Last Level Cache (LLC) is a key element to improve application performance in multi-cores. To handle the worst case, the main design trend employs tiled architectures with a large LLC organized in banks, which goes underutilized in several realistic scenarios. Our proposal, named\n            <jats:italic>DarkCache<\/jats:italic>\n            , aims at properly powering off such unused banks to optimize the Energy-Delay Product (EDP) through an adaptive cache reconfiguration, thus aggressively reducing the leakage energy. The implemented solution is general and it can recognize and skip the activation of the\n            <jats:italic>DarkCache<\/jats:italic>\n            policy for the few strong memory intensive applications that actually require the use of the entire LLC. The validation has been carried out on 16- and 64-core architectures also accounting for two state-of-the-art methodologies. Compared to the baseline solution,\n            <jats:italic>DarkCache<\/jats:italic>\n            exhibits a performance overhead within 2% and an average EDP improvement of 32.58% and 36.41% considering 16 and 64 cores, respectively. Moreover,\n            <jats:italic>DarkCache<\/jats:italic>\n            shows an average EDP gain between 16.15% (16 cores) and 21.05% (64 cores) compared to the best state-of-the-art we evaluated, and it confirms a good scalability since the gain improves with the size of the architecture.\n          <\/jats:p>","DOI":"10.1145\/3186895","type":"journal-article","created":{"date-parts":[[2018,5,1]],"date-time":"2018-05-01T12:00:39Z","timestamp":1525176039000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["DarkCache"],"prefix":"10.1145","volume":"15","author":[{"given":"Davide","family":"Zoni","sequence":"first","affiliation":[{"name":"Politecnico di Milano, Via Ponzio, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Colombo","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Via Ponzio, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"William","family":"Fornaciari","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Via Ponzio, Milano, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2017.06.001"},{"volume-title":"Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA\u201916)","author":"Beckmann N.","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"e_1_2_1_6_1","first-page":"1","article-title":"Avoiding message-dependent deadlock in network-based systems on chip.VLSI Design 2007","volume":"95859","author":"Hansson Andreas","year":"2007","journal-title":"Article ID"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"volume-title":"Transactions on","author":"Kotera Isao","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.03.008"},{"volume-title":"Proceedings of the 2012 39th Annual International Symposium on Computer Architecture (ISCA\u201912)","author":"Manikantan R.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2278289"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.160"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.2"},{"volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS\u201915)","author":"Nilakantan S.","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339685"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165581"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.19"},{"key":"e_1_2_1_21_1","doi-asserted-by":"crossref","unstructured":"Daniel J. Sorin Mark D. Hill and David A. Wood. 2011. A Primer on Memory Consistency and Cache Coherence. Morgan 8 Claypool.   Daniel J. Sorin Mark D. Hill and David A. Wood. 2011. A Primer on Memory Consistency and Cache Coherence. Morgan 8 Claypool.","DOI":"10.1007\/978-3-031-01733-9"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"volume-title":"Proceedings of the 2013 IEEE 31st International Conference on Computer Design (ICCD\u201913)","author":"Sundararajan K. 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