{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T08:22:24Z","timestamp":1759134144086,"version":"3.41.0"},"reference-count":48,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2018,5,22]],"date-time":"2018-05-22T00:00:00Z","timestamp":1526947200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Ministry of Science, ICT 8 Future Planning","award":["NRF-2015M3C4A7065522"],"award-info":[{"award-number":["NRF-2015M3C4A7065522"]}]},{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Next-Generation Information Computing Development Program"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2018,5,31]]},"abstract":"<jats:p>This article proposes a new phase change memory\u2013 (PCM) based memory storage architecture with associated self-adaptive data filtering for various embedded devices to support energy efficiency as well as high computing power. In this approach, PCM-based memory storage can be used as working memory and mass storage layers simultaneously, and a self-adaptive data filtering module composed of small DRAM dual buffers was designed to improve unfavorable PCM features, such as asymmetric read\/write access latencies and limited endurance and enhance spatial\/temporal localities. In particular, the self-adaptive data filtering algorithm enhances data reusability by screening potentially high reusable data and predicting adequate lifetime of those data depending on current victim time decision value. We also propose the possibility that a small amount of DRAM buffer is embedded into mobile processors, keeping this as small as possible for cost effectiveness and energy efficiency. Experimental results show that by exploiting a small amount of DRAM space for dual buffers and using the self-adaptive filtering algorithm to manage them, the proposed system can reduce execution time by a factor of 1.9 compared to the unified conventional model with same the DRAM capacity and can be considered comparable to 1.5\u00d7 DRAM capacity.<\/jats:p>","DOI":"10.1145\/3190856","type":"journal-article","created":{"date-parts":[[2018,5,23]],"date-time":"2018-05-23T15:08:42Z","timestamp":1527088122000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Self-Adaptive Filtering Algorithm with PCM-Based Memory Storage System"],"prefix":"10.1145","volume":"17","author":[{"given":"Su-Kyung","family":"Yoon","sequence":"first","affiliation":[{"name":"Yonsei University, Seodaemun-gu, Seoul"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jitae","family":"Yun","sequence":"additional","affiliation":[{"name":"Yonsei University, Seodaemun-gu, Seoul"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung-Geun","family":"Kim","sequence":"additional","affiliation":[{"name":"Yonsei University, Seodaemun-gu, Seoul"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2642-6662","authenticated-orcid":false,"given":"Shin-Dug","family":"Kim","sequence":"additional","affiliation":[{"name":"Yonsei University, Seodaemun-gu, Seoul"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,5,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968456.2974004"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2699343.2699344"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2011.6008591"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627647"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2631641"},{"volume-title":"Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits\u201915)","author":"Ueki M.","key":"e_1_2_1_6_1","unstructured":"M. Ueki , K. Takeuchi , T. Yamamoto , A. Tanabe , N. Ikarashi , M. Saitoh , T. Nagumo , H. Sunamura , M. Narihiro , K. Uejima , K. Masuzaki , N. Furutake , S. Saito , Y. Yabe , A. Mitsuiki , K. Takeda , T. Hase , and Y. Hayashi . 2015. Low-power embedded ReRAM technology for IoT applications . In Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits\u201915) . IEEE, 108--109. M. Ueki, K. Takeuchi, T. Yamamoto, A. Tanabe, N. Ikarashi, M. Saitoh, T. Nagumo, H. Sunamura, M. Narihiro, K. Uejima, K. Masuzaki, N. Furutake, S. Saito, Y. Yabe, A. Mitsuiki, K. Takeda, T. Hase, and Y. Hayashi. 2015. Low-power embedded ReRAM technology for IoT applications. In Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits\u201915). IEEE, 108--109."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757392"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.81"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555758"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555760"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2016.07.006"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/279361.279404"},{"key":"e_1_2_1_13_1","unstructured":"Pin Tool Instrumentation Tool. Retrieved from http:\/\/www.pintool.org.  Pin Tool Instrumentation Tool. Retrieved from http:\/\/www.pintool.org."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_15_1","unstructured":"MediaBench. Retrieved from http:\/\/euler.slu.edu\/\u223cfritts\/mediabench\/.  MediaBench. Retrieved from http:\/\/euler.slu.edu\/\u223cfritts\/mediabench\/."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165675"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2394303"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.52"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2644865.2541957"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592814"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1961295.1950379"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1871147"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2738053"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2538229"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815981"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.9"},{"key":"e_1_2_1_28_1","volume-title":"CAUSE: Critical application usage-aware memory system using non-volatile memory for mobile devices. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design","author":"Kim Yeseong","year":"2015","unstructured":"Kim Yeseong et al. 2015 . CAUSE: Critical application usage-aware memory system using non-volatile memory for mobile devices. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design . IEEE Press , 690--696. Kim Yeseong et al. 2015. CAUSE: Critical application usage-aware memory system using non-volatile memory for mobile devices. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. IEEE Press, 690--696."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2495264"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2455972"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2586059"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.40"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC\u201911)","author":"Xiangyu Dong","year":"2011","unstructured":"Dong Xiangyu and Yuan Xie . 2011 . AdaMS: Adaptive MLC\/SLC phase-change memory design for file storage . Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC\u201911) . Dong Xiangyu and Yuan Xie. 2011. AdaMS: Adaptive MLC\/SLC phase-change memory design for file storage. Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC\u201911)."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2668128"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024163"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669118"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.62"},{"key":"e_1_2_1_39_1","doi-asserted-by":"crossref","first-page":"2852","DOI":"10.1093\/comjnl\/bxu133","article-title":"Data classification management with its interfacing structure for hybrid SLC\/MLC PRAM main memory","volume":"58","author":"Sung-In Jang","year":"2014","unstructured":"Jang Sung-In 2014 . Data classification management with its interfacing structure for hybrid SLC\/MLC PRAM main memory . Comput J. 58 , 11 (2014), 2852 -- 2863 . Jang Sung-In et al. 2014. Data classification management with its interfacing structure for hybrid SLC\/MLC PRAM main memory. Comput J. 58, 11 (2014), 2852--2863.","journal-title":"Comput J."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503221"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168941"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485960"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"volume-title":"Proceedings of the 2015 International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201915)","author":"Chun-Ta","key":"e_1_2_1_44_1","unstructured":"Chun-Ta Lin et al. 2015. How to improve the space utilization of dedup-based PCM storage devices? In Proceedings of the 2015 International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201915) . IEEE, 11--20. Chun-Ta Lin et al. 2015. How to improve the space utilization of dedup-based PCM storage devices? In Proceedings of the 2015 International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201915). IEEE, 11--20."},{"volume-title":"Proceedings of the 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC\u201913)","author":"Liu","key":"e_1_2_1_45_1","unstructured":"Liu Duo et al. 2013. Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems . In Proceedings of the 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC\u201913) . IEEE, 279--284. Liu Duo et al. 2013. Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems. In Proceedings of the 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC\u201913). IEEE, 279--284."},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2656045.2656049"},{"volume-title":"Proceedings of the 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA\u201915)","author":"Lin","key":"e_1_2_1_47_1","unstructured":"Lin Ye-Jyun et al. 2015. A buffer cache architecture for smartphones with hybrid DRAM\/PCM memory . In Proceedings of the 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA\u201915) . IEEE, 1--6. Lin Ye-Jyun et al. 2015. A buffer cache architecture for smartphones with hybrid DRAM\/PCM memory. In Proceedings of the 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA\u201915). IEEE, 1--6."},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597924"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3190856","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3190856","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:51Z","timestamp":1750213611000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3190856"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,22]]},"references-count":48,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,5,31]]}},"alternative-id":["10.1145\/3190856"],"URL":"https:\/\/doi.org\/10.1145\/3190856","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2018,5,22]]},"assertion":[{"value":"2017-05-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-05-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}