{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T03:10:06Z","timestamp":1775790606200,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":54,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,11]],"date-time":"2018-06-11T00:00:00Z","timestamp":1528675200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-sa\/4.0\/"}],"funder":[{"name":"EPSRC","award":["EP\/K034448\/1"],"award-info":[{"award-number":["EP\/K034448\/1"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,11]]},"DOI":"10.1145\/3192366.3192373","type":"proceedings-article","created":{"date-parts":[[2018,6,12]],"date-time":"2018-06-12T08:16:01Z","timestamp":1528791361000},"page":"211-225","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["The semantics of transactions and weak memory in x86, Power, ARM, and C++"],"prefix":"10.1145","author":[{"given":"Nathan","family":"Chong","sequence":"first","affiliation":[{"name":"ARM, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tyler","family":"Sorensen","sequence":"additional","affiliation":[{"name":"Imperial College London, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Wickerson","sequence":"additional","affiliation":[{"name":"Imperial College London, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,6,11]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593241"},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325100"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_25"},{"key":"e_1_3_2_2_4_1","volume-title":"Litmus: Running Tests Against Hardware. In Int. Conf. on Tools and Algorithms for Construction and Analysis of Systems (TACAS).","author":"Alglave Jade","year":"2011","unstructured":"Jade Alglave , Luc Maranget , Susmit Sarkar , and Peter Sewell . 2011 . Litmus: Running Tests Against Hardware. In Int. Conf. on Tools and Algorithms for Construction and Analysis of Systems (TACAS). Jade Alglave, Luc Maranget, Susmit Sarkar, and Peter Sewell. 2011. Litmus: Running Tests Against Hardware. In Int. Conf. on Tools and Algorithms for Construction and Analysis of Systems (TACAS)."},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627752"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"crossref","unstructured":"Jade Alglave Luc Maranget and Michael Tautschnig. 2014. Herding cats: modelling simulation testing and data-mining for weak memory (online companion material). (2014). http:\/\/moscova.inria.fr\/ ~maranget\/cats\/model-power\/all.html#sec4 .  Jade Alglave Luc Maranget and Michael Tautschnig. 2014. Herding cats: modelling simulation testing and data-mining for weak memory (online companion material). (2014). http:\/\/moscova.inria.fr\/ ~maranget\/cats\/model-power\/all.html#sec4 .","DOI":"10.1145\/2594291.2594347"},{"key":"e_1_3_2_2_7_1","unstructured":"ARM. 2017. ARMv8 Architecture Reference Manual. https:\/\/static.docs. arm.com\/ddi0487\/b\/DDI0487B_a_armv8_arm.pdf  ARM. 2017. ARMv8 Architecture Reference Manual. https:\/\/static.docs. arm.com\/ddi0487\/b\/DDI0487B_a_armv8_arm.pdf"},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429069.2429099"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2837614.2837637"},{"key":"e_1_3_2_2_10_1","volume-title":"The Problem of Programming Language Concurrency Semantics. In Europ. Symp. on Programming (ESOP).","author":"Batty Mark","year":"2015","unstructured":"Mark Batty , Kayvan Memarian , Kyndylan Nienhuis , Jean PichonPharabod , and Peter Sewell . 2015 . The Problem of Programming Language Concurrency Semantics. In Europ. Symp. on Programming (ESOP). Mark Batty, Kayvan Memarian, Kyndylan Nienhuis, Jean PichonPharabod, and Peter Sewell. 2015. The Problem of Programming Language Concurrency Semantics. In Europ. Symp. on Programming (ESOP)."},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2006.18"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1375581.1375591"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3062341.3062353"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485942"},{"key":"e_1_3_2_2_16_1","volume-title":"Int. Conf. on Concurrency Theory (CONCUR).","author":"Cerone Andrea","year":"2015","unstructured":"Andrea Cerone , Giovanni Bernardi , and Alexey Gotsman . 2015 . A Framework for Transactional Consistency Models with Atomic Visibility . In Int. Conf. on Concurrency Theory (CONCUR). Andrea Cerone, Giovanni Bernardi, and Alexey Gotsman. 2015. A Framework for Transactional Consistency Models with Atomic Visibility. In Int. Conf. on Concurrency Theory (CONCUR)."},{"key":"e_1_3_2_2_17_1","volume-title":"Int. Symp. on High Performance Computer Architecture (HPCA).","author":"Chung JaeWoong","year":"2008","unstructured":"JaeWoong Chung , Michael Dalton , Hari Kannan , and Christos Kozyrakis . 2008 . Thread-Safe Dynamic Binary Translation using Transactional Memory . In Int. Symp. on High Performance Computer Architecture (HPCA). JaeWoong Chung, Michael Dalton, Hari Kannan, and Christos Kozyrakis. 2008. Thread-Safe Dynamic Binary Translation using Transactional Memory. In Int. Symp. on High Performance Computer Architecture (HPCA)."},{"key":"e_1_3_2_2_18_1","volume-title":"Reasoning about Parallel Architectures","author":"Collier William W.","unstructured":"William W. Collier . 1992. Reasoning about Parallel Architectures . Prentice Hall . William W. Collier. 1992. Reasoning about Parallel Architectures. Prentice Hall."},{"key":"e_1_3_2_2_19_1","volume-title":"ACM Workshop on Transactional Computing (TRANSACT). http:\/\/transact09","author":"Dalessandro Luke","unstructured":"Luke Dalessandro and Michael L. Scott . 2009. Strong Isolation is a Weak Idea . In ACM Workshop on Transactional Computing (TRANSACT). http:\/\/transact09 .cs.washington.edu\/33_paper.pdf Luke Dalessandro and Michael L. Scott. 2009. Strong Isolation is a Weak Idea. In ACM Workshop on Transactional Computing (TRANSACT). http:\/\/transact09.cs.washington.edu\/33_paper.pdf"},{"key":"e_1_3_2_2_20_1","volume-title":"Int. Conf. on Distributed Computing (DISC).","author":"Dalessandro Luke","unstructured":"Luke Dalessandro , Michael L. Scott , and Michael F. Spear . 2010. Transactions as the Foundation of a Memory Consistency Model . In Int. Conf. on Distributed Computing (DISC). Luke Dalessandro, Michael L. Scott, and Michael F. Spear. 2010. Transactions as the Foundation of a Memory Consistency Model. In Int. Conf. on Distributed Computing (DISC)."},{"key":"e_1_3_2_2_21_1","unstructured":"Will Deacon. 2016. The ARMv8 Application Level Memory Model. https:\/\/github.com\/herd\/herdtools7\/blob\/master\/herd\/libdir\/ aarch64.cat . (2016).  Will Deacon. 2016. The ARMv8 Application Level Memory Model. https:\/\/github.com\/herd\/herdtools7\/blob\/master\/herd\/libdir\/ aarch64.cat . (2016)."},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508263"},{"key":"e_1_3_2_2_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3158106"},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2837614.2837615"},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1178597.1178609"},{"key":"e_1_3_2_2_26_1","volume-title":"Broadwell CP Us. PCWorld (August","author":"Hachman Mark","year":"2014","unstructured":"Mark Hachman . 2014. Intel finds specialized TSX enterprise bug on Haswell , Broadwell CP Us. PCWorld (August 2014 ). http:\/\/www. pcworld.com\/article\/2464880 Mark Hachman. 2014. Intel finds specialized TSX enterprise bug on Haswell, Broadwell CP Us. PCWorld (August 2014). http:\/\/www. pcworld.com\/article\/2464880"},{"key":"e_1_3_2_2_27_1","volume-title":"Transactional Memory","author":"Harris Tim","unstructured":"Tim Harris , James Larus , and Ravi Rajwar . 2010. Transactional Memory ( 2 nd ed.). Morgan &amp; Claypool . Tim Harris, James Larus, and Ravi Rajwar. 2010. Transactional Memory (2nd ed.). Morgan &amp; Claypool.","edition":"2"},{"key":"e_1_3_2_2_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_2_29_1","unstructured":"IBM. 2015. Power ISA (Version 3.0).  IBM. 2015. Power ISA (Version 3.0)."},{"key":"e_1_3_2_2_30_1","volume-title":"6th Generation Intel Processor Family: Specification Update. (June","year":"2017","unstructured":"Intel. 2017. 6th Generation Intel Processor Family: Specification Update. (June 2017 ). https:\/\/www3.intel.com\/content\/ dam\/www\/public\/us\/en\/documents\/specification-updates\/ desktop-6th-gen-core-family-spec-update.pdf Intel. 2017. 6th Generation Intel Processor Family: Specification Update. (June 2017). https:\/\/www3.intel.com\/content\/ dam\/www\/public\/us\/en\/documents\/specification-updates\/ desktop-6th-gen-core-family-spec-update.pdf"},{"key":"e_1_3_2_2_31_1","unstructured":"Intel. 2017. Intel 64 and IA-32 Architectures: Software Developer\u2019s Manual. https:\/\/software.intel.com\/en-us\/articles\/intel-sdm  Intel. 2017. Intel 64 and IA-32 Architectures: Software Developer\u2019s Manual. https:\/\/software.intel.com\/en-us\/articles\/intel-sdm"},{"key":"e_1_3_2_2_32_1","volume-title":"Transactional Synchronization in Haswell. (February","author":"Zone Intel Developer","year":"2012","unstructured":"Intel Developer Zone . 2012. Transactional Synchronization in Haswell. (February 2012 ). https:\/\/software.intel.com\/en-us\/blogs\/2012\/02\/07\/ transactional-synchronization-in-haswell Intel Developer Zone. 2012. Transactional Synchronization in Haswell. (February 2012). https:\/\/software.intel.com\/en-us\/blogs\/2012\/02\/07\/ transactional-synchronization-in-haswell"},{"key":"e_1_3_2_2_33_1","unstructured":"ISO\/IEC. 2011. Programming languages \u2013 C++. International standard 14882:2011.  ISO\/IEC. 2011. Programming languages \u2013 C++. International standard 14882:2011."},{"key":"e_1_3_2_2_34_1","unstructured":"ISO\/IEC. 2015. Technical Specification for C++ Extensions for Transactional Memory. Draft technical specification. http:\/\/www.open-std. org\/jtc1\/sc22\/wg21\/docs\/papers\/2015\/n4514.pdf  ISO\/IEC. 2015. Technical Specification for C++ Extensions for Transactional Memory. Draft technical specification. http:\/\/www.open-std. org\/jtc1\/sc22\/wg21\/docs\/papers\/2015\/n4514.pdf"},{"key":"e_1_3_2_2_35_1","volume-title":"Software Abstractions \u2013 Logic, Language, and Analysis (revised ed.)","author":"Jackson Daniel","unstructured":"Daniel Jackson . 2012. Software Abstractions \u2013 Logic, Language, and Analysis (revised ed.) . MIT Press . Daniel Jackson. 2012. Software Abstractions \u2013 Logic, Language, and Analysis (revised ed.). MIT Press."},{"key":"e_1_3_2_2_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3158105"},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/3062341.3062352"},{"key":"e_1_3_2_2_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"e_1_3_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037723"},{"key":"e_1_3_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.entcs.2007.04.009"},{"key":"e_1_3_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152177"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2983990.2983997"},{"key":"e_1_3_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03359-9_27"},{"key":"e_1_3_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3158107"},{"key":"e_1_3_2_2_46_1","volume-title":"Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Int. Symp. on Microarchitecture (MICRO).","author":"Rajwar Ravi","unstructured":"Ravi Rajwar and James R. Goodman . 2001 . Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Int. Symp. on Microarchitecture (MICRO). Ravi Rajwar and James R. Goodman. 2001. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Int. Symp. on Microarchitecture (MICRO)."},{"key":"e_1_3_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254102"},{"key":"e_1_3_2_2_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993520"},{"key":"e_1_3_2_2_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/42190.42277"},{"key":"e_1_3_2_2_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1583991.1584012"},{"key":"e_1_3_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250744"},{"key":"e_1_3_2_2_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/2983990.2984032"},{"key":"e_1_3_2_2_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2555306"},{"key":"e_1_3_2_2_54_1","volume-title":"I: User-Level ISA (version 2.2)","author":"Waterman Andrew","year":"2017","unstructured":"Andrew Waterman and Krste Asanovi\u0107 (Eds.). 2017 . The RISC-V Instruction Set Manual , Volume I: User-Level ISA (version 2.2) . RISC-V Foundation . https:\/\/riscv.org\/specifications\/ Andrew Waterman and Krste Asanovi\u0107 (Eds.). 2017. The RISC-V Instruction Set Manual, Volume I: User-Level ISA (version 2.2). RISC-V Foundation. https:\/\/riscv.org\/specifications\/"},{"key":"e_1_3_2_2_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/3009837.3009838"},{"key":"e_1_3_2_2_56_1","unstructured":"Michael Wong. 2014. Transactional Language Constructs for C++. In C++ Conference (CppCon). http:\/\/bit.ly\/2tWk4uz  Michael Wong. 2014. Transactional Language Constructs for C++. In C++ Conference (CppCon). http:\/\/bit.ly\/2tWk4uz"}],"event":{"name":"PLDI '18: ACM SIGPLAN Conference on Programming Language Design and Implementation","location":"Philadelphia PA USA","acronym":"PLDI '18","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"]},"container-title":["Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3192366.3192373","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3192366.3192373","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T22:07:53Z","timestamp":1750198073000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3192366.3192373"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,11]]},"references-count":54,"alternative-id":["10.1145\/3192366.3192373","10.1145\/3192366"],"URL":"https:\/\/doi.org\/10.1145\/3192366.3192373","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/3296979.3192373","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2018,6,11]]},"assertion":[{"value":"2018-06-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}