{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:36:18Z","timestamp":1750221378756,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,5,30]],"date-time":"2018-05-30T00:00:00Z","timestamp":1527638400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,5,30]]},"DOI":"10.1145\/3194554.3194573","type":"proceedings-article","created":{"date-parts":[[2018,6,7]],"date-time":"2018-06-07T13:57:46Z","timestamp":1528379866000},"page":"237-242","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["AB-Aware"],"prefix":"10.1145","author":[{"given":"Suhit","family":"Pai","sequence":"first","affiliation":[{"name":"Indian Institute of Technology, Bombay, Mumbai, India"}]},{"given":"Newton","family":"Singh","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Bombay, Mumbai, India"}]},{"given":"Virendra","family":"Singh","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Bombay, Mumbai, India"}]}],"member":"320","published-online":{"date-parts":[[2018,5,30]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","unstructured":"Aamer Jaleel William Hasenplaugh Moinuddin Qureshi Julien Sebot Simon Steely Jr. and Joel Emer. 2008. Adaptive Insertion Policies for Managing Shared Caches. In PACT-17. 208--219. 10.1145\/1454115.1454145","DOI":"10.1145\/1454115.1454145"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","unstructured":"Aamer Jaleel Kevin B. Theobald Simon C. Steely Jr. and Joel Emer. 2010. High Performance Cache Replacement Using Rereference Interval Prediction (RRIP). In ISCA-37. 60--71. 10.1145\/1815961.1815971","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","unstructured":"P. Lathigara S. Balachandran and V. Singh. 2015. Application Behavior Aware Re-reference Interval Prediction for Shared LLC. In ICCD-33. 172--179. 10.1109\/ICCD.2015.7357099","DOI":"10.1109\/ICCD.2015.7357099"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","unstructured":"Harish Patil Robert Cohn Mark Charney Rajiv Kapoor Andrew Sun and Anand Karunanidhi. 2004. Pinpointing Representative Portions of Large Intel\u00ae Itanium\u00ae Programs with Dynamic Instrumentation. In Micro-37. 81--92. 10.1109\/MICRO.2004.28","DOI":"10.1109\/MICRO.2004.28"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","unstructured":"Moinuddin K. Qureshi Aamer Jaleel Yale N. Patt Simon C. Steely and Joel Emer. 2007. Adaptive Insertion Policies for High Performance Caching. In ISCA-34. 381--391. 10.1145\/1250662.1250709","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","unstructured":"Carole-Jean Wu Aamer Jaleel Margaret Martonosi Simon C. Steely Jr. and Joel Emer. 2011. PACMan: Prefetch-aware Cache Management for High Performance Caching. In Micro-44. 10.1145\/2155620.2155672","DOI":"10.1145\/2155620.2155672"}],"event":{"name":"GLSVLSI '18: Great Lakes Symposium on VLSI 2018","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Chicago IL USA","acronym":"GLSVLSI '18"},"container-title":["Proceedings of the 2018 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3194554.3194573","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3194554.3194573","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:47Z","timestamp":1750213607000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3194554.3194573"}},"subtitle":["Application Behavior Aware Management of Shared Last Level Caches"],"short-title":[],"issued":{"date-parts":[[2018,5,30]]},"references-count":12,"alternative-id":["10.1145\/3194554.3194573","10.1145\/3194554"],"URL":"https:\/\/doi.org\/10.1145\/3194554.3194573","relation":{},"subject":[],"published":{"date-parts":[[2018,5,30]]},"assertion":[{"value":"2018-05-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}