{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:36:18Z","timestamp":1750221378769,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,5,30]],"date-time":"2018-05-30T00:00:00Z","timestamp":1527638400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,5,30]]},"DOI":"10.1145\/3194554.3194592","type":"proceedings-article","created":{"date-parts":[[2018,6,7]],"date-time":"2018-06-07T13:57:46Z","timestamp":1528379866000},"page":"99-104","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Impolite High Speed Interfaces with Asynchronous Pulse Logic"],"prefix":"10.1145","author":[{"given":"Merritt","family":"Miller","sequence":"first","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA, USA"}]},{"given":"Carrie","family":"Segal","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA, USA"}]},{"given":"David","family":"Mc Carthy","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA, USA"}]},{"given":"Aditya","family":"Dalakoti","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA, USA"}]},{"given":"Prashansa","family":"Mukim","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA, USA"}]},{"given":"Forrest","family":"Brewer","sequence":"additional","affiliation":[{"name":"Univeristy of California, Santa Barbara, Santa Barbara, CA, USA"}]}],"member":"320","published-online":{"date-parts":[[2018,5,30]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/785167.785351"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/784892.784966"},{"key":"e_1_3_2_1_3_1","volume-title":"ISCAS","author":"Jung Gunok","year":"2002","unstructured":"Gunok Jung, V.A. Sundarajan, and G.E. Sobelman. A robust self-resetting cmos 32-bit parallel adder. In ISCAS 2002."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/786453.786721"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/244522.244542"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/572586"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922205"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/785168.785364"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.28"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542107"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009952"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223730"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/551495.785271"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/646705.702186"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.82"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.105130"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127956"},{"key":"e_1_3_2_1_20_1","first-page":"1","volume-title":"Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on","author":"Wang Peng","year":"2014","unstructured":"Peng Wang, Ziqiang Wang, Chun Zhang, and Zhihua Wang. Data lane design for transmitter of 4.8 gbps serdes in 65nm cmos. In Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on, pages 1--2. IEEE, 2014."},{"key":"e_1_3_2_1_21_1","first-page":"206","volume-title":"VLSI Circuits (VLSIC), 2011 Symposium on","author":"Proesel Jonathan E","year":"2011","unstructured":"Jonathan E Proesel and Timothy O Dickson. A 20-gb\/s, 0.66-pj\/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm soi cmos. In VLSI Circuits (VLSIC), 2011 Symposium on, pages 206--207. IEEE, 2011."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665747"}],"event":{"name":"GLSVLSI '18: Great Lakes Symposium on VLSI 2018","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Chicago IL USA","acronym":"GLSVLSI '18"},"container-title":["Proceedings of the 2018 Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3194554.3194592","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3194554.3194592","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:47Z","timestamp":1750213607000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3194554.3194592"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,30]]},"references-count":22,"alternative-id":["10.1145\/3194554.3194592","10.1145\/3194554"],"URL":"https:\/\/doi.org\/10.1145\/3194554.3194592","relation":{},"subject":[],"published":{"date-parts":[[2018,5,30]]},"assertion":[{"value":"2018-05-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}