{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:36:12Z","timestamp":1750221372475,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,24]],"date-time":"2018-06-24T00:00:00Z","timestamp":1529798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,24]]},"DOI":"10.1145\/3195970.3195984","type":"proceedings-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T13:54:59Z","timestamp":1529416499000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Active forwarding"],"prefix":"10.1145","author":[{"given":"Hsueh-Chun","family":"Fu","sequence":"first","affiliation":[{"name":"National Taiwan University, Taipei City, Taiwan, R.O.C"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Po-Han","family":"Wang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei City, Taiwan, R.O.C"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia-Lin","family":"Yang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei City, Taiwan, R.O.C"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Intel Virtualization Technology for Directed I\/O. Intel technology journal 10, 3","author":"Abramson Darren","year":"2006","unstructured":"Darren Abramson , Jeff Jackson , Sridhar Muthrasanallur , Gil Neiger , Greg Regnier , Rajesh Sankaran , Ioannis Schoinas , Rich Uhlig , Balaji Vembu , and John Wiegert . 2006. Intel Virtualization Technology for Directed I\/O. Intel technology journal 10, 3 ( 2006 ). Darren Abramson, Jeff Jackson, Sridhar Muthrasanallur, Gil Neiger, Greg Regnier, Rajesh Sankaran, Ioannis Schoinas, Rich Uhlig, Balaji Vembu, and John Wiegert. 2006. Intel Virtualization Technology for Directed I\/O. Intel technology journal 10, 3 (2006)."},{"unstructured":"AMD. 2007. AMD I\/O Virtualization Technology (IOMMU) Specification. (2007).  AMD. 2007. AMD I\/O Virtualization Technology (IOMMU) Specification. (2007).","key":"e_1_3_2_1_2_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1145\/1815961.1815970"},{"volume-title":"Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)","author":"Basu Arkaprava","unstructured":"Arkaprava Basu , Mark D. Hill , and Michael M. Swift . 2012. Reducing Memory Reference Energy with Opportunistic Virtual Caching . In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12) . 297--308. Arkaprava Basu, Mark D. Hill, and Michael M. Swift. 2012. Reducing Memory Reference Energy with Opportunistic Virtual Caching. In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12). 297--308.","key":"e_1_3_2_1_4_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1145\/1346281.1346286"},{"volume-title":"Advanced ASIC Chip Synthesis: Using Synopsys\u00ae Design CompilerTM Physical CompilerTM and PrimeTime\u00ae","author":"Bhatnagar Himanshu","unstructured":"Himanshu Bhatnagar . 2007. Advanced ASIC Chip Synthesis: Using Synopsys\u00ae Design CompilerTM Physical CompilerTM and PrimeTime\u00ae . Springer Science & Business Media . Himanshu Bhatnagar. 2007. Advanced ASIC Chip Synthesis: Using Synopsys\u00ae Design CompilerTM Physical CompilerTM and PrimeTime\u00ae. Springer Science & Business Media.","key":"e_1_3_2_1_6_1"},{"volume-title":"Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6. 195--205","author":"Chatterjee S.","unstructured":"S. Chatterjee and S. Sen . 2000. Cache-efficient matrix transposition . In Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6. 195--205 . S. Chatterjee and S. Sen. 2000. Cache-efficient matrix transposition. In Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6. 195--205.","key":"e_1_3_2_1_7_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1145\/2830772.2830798"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1145\/2897937.2897972"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.5555\/2840819.2840873"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1145\/2000064.2000108"},{"unstructured":"HSA Foundation. 2015. HSA Platform System Architecture. (2015).  HSA Foundation. 2015. HSA Platform System Architecture. (2015).","key":"e_1_3_2_1_12_1"},{"key":"e_1_3_2_1_13_1","volume":"201","author":"Hao Y.","unstructured":"Y. Hao , Z. Fang , G. Reinman , and J. Cong. 201 7. Supporting Address Translation for Accelerator-Centric Architectures. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). 37--48. Y. Hao, Z. Fang, G. Reinman, and J. Cong. 2017. Supporting Address Translation for Accelerator-Centric Architectures. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). 37--48.","journal-title":"J. Cong."},{"volume-title":"2014 IEEE International Symposium on Workload Characterization (IISWC). 110--119","author":"Reagen B.","unstructured":"B. Reagen , R. Adolf , Y. S. Shao , G. Y. Wei , and D. Brooks . 2014. MachSuite: Benchmarks for accelerator design and customized architectures . In 2014 IEEE International Symposium on Workload Characterization (IISWC). 110--119 . B. Reagen, R. Adolf, Y. S. Shao, G. Y. Wei, and D. Brooks. 2014. MachSuite: Benchmarks for accelerator design and customized architectures. In 2014 IEEE International Symposium on Workload Characterization (IISWC). 110--119.","key":"e_1_3_2_1_14_1"},{"unstructured":"Yakun Sophia Shao and David Brooks. 2015. Research Infrastructures for Hardware Accelerators. Morgan & Claypool. 99-- pages.  Yakun Sophia Shao and David Brooks. 2015. Research Infrastructures for Hardware Accelerators . Morgan & Claypool. 99-- pages.","key":"e_1_3_2_1_15_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.5555\/2665671.2665689"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.5555\/3195638.3195697"},{"volume-title":"Keynote at the 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO).","author":"Sodani Avinash","unstructured":"Avinash Sodani . 2011. Race to exascale: Opportunities and challenges . In Keynote at the 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). Avinash Sodani. 2011. Race to exascale: Opportunities and challenges. In Keynote at the 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO).","key":"e_1_3_2_1_18_1"},{"key":"e_1_3_2_1_19_1","volume-title":"Jung Ho Ahn, and Norman P Jouppi","author":"Thoziyoor Shyamkumar","year":"2008","unstructured":"Shyamkumar Thoziyoor , Naveen Muralimanohar , Jung Ho Ahn, and Norman P Jouppi . 2008 . CACTI 5.1. Technical Report. HPL-2008-20, HP Labs . Shyamkumar Thoziyoor, Naveen Muralimanohar, Jung Ho Ahn, and Norman P Jouppi. 2008. CACTI 5.1. Technical Report. HPL-2008-20, HP Labs."}],"event":{"sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)","SIGBED ACM Special Interest Group on Embedded Systems"],"acronym":"DAC '18","name":"DAC '18: The 55th Annual Design Automation Conference 2018","location":"San Francisco California"},"container-title":["Proceedings of the 55th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3195984","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3195984","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:35Z","timestamp":1750213595000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3195984"}},"subtitle":["eliminate IOMMU address translation for accelerator-rich architectures"],"short-title":[],"issued":{"date-parts":[[2018,6,24]]},"references-count":19,"alternative-id":["10.1145\/3195970.3195984","10.1145\/3195970"],"URL":"https:\/\/doi.org\/10.1145\/3195970.3195984","relation":{},"subject":[],"published":{"date-parts":[[2018,6,24]]},"assertion":[{"value":"2018-06-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}