{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:33:10Z","timestamp":1750221190166,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,24]],"date-time":"2018-06-24T00:00:00Z","timestamp":1529798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217738"],"award-info":[{"award-number":["CCF-1217738"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,24]]},"DOI":"10.1145\/3195970.3196007","type":"proceedings-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T13:54:59Z","timestamp":1529416499000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["CASTLE"],"prefix":"10.1145","author":[{"given":"Poovaiah M.","family":"Palangappa","sequence":"first","affiliation":[{"name":"University of Pittsburgh"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_2_1","volume-title":"IEDM","author":"Baek I. G.","year":"2004","unstructured":"I. G. Baek scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses,\" in Proc . IEDM , 2004 . I. G. Baek et al., \"Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses,\" in Proc. IEDM, 2004."},{"key":"e_1_3_2_1_3_1","unstructured":"\"International technology roadmap for semiconductors \" 2011.  \"International technology roadmap for semiconductors \" 2011."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956575"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.80"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSAC.2006.21"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136502"},{"key":"e_1_3_2_1_8_1","volume-title":"ISCAS","author":"Yang B.","year":"2010","unstructured":"B. Yang low power phase change random access memory using a data-comparison write scheme,\" in Proc . ISCAS , 2010 . B. Yang et al., \"A low power phase change random access memory using a data-comparison write scheme,\" in Proc. ISCAS, 2010."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"e_1_3_2_1_10_1","volume-title":"DSN","author":"Kong J.","year":"2010","unstructured":"J. Kong and H. Zhou , \" Improving privacy and lifetime of PCM-based main memory,\" in Proc . DSN , 2010 . J. Kong and H. Zhou, \"Improving privacy and lifetime of PCM-based main memory,\" in Proc. DSN, 2010."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694387"},{"key":"e_1_3_2_1_12_1","volume-title":"ICCD","author":"Niu D.","year":"2013","unstructured":"D. Niu power multi-level-cell resistive memory design with incomplete data mapping,\" in Proc . ICCD , 2013 . D. Niu et al., \"Low power multi-level-cell resistive memory design with incomplete data mapping,\" in Proc. ICCD, 2013."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446056"},{"key":"e_1_3_2_1_14_1","volume-title":"Frequent pattern compression: A significance-based compression scheme for L2 caches","author":"Alameldeen A.","year":"2004","unstructured":"A. Alameldeen and D. Wood , \" Frequent pattern compression: A significance-based compression scheme for L2 caches ,\" 2004 . Univ. Wisconsin-Madison TR 1500. A. Alameldeen and D. Wood, \"Frequent pattern compression: A significance-based compression scheme for L2 caches,\" 2004. Univ. Wisconsin-Madison TR1500."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"volume-title":"CPU2006","year":"2006","key":"e_1_3_2_1_18_1","unstructured":"\"SPEC CPU2006 ,\" 2006 . \"SPEC CPU2006,\" 2006."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"R. B. Lee \"Security basics for computer architects \" Synthesis Lectures on Computer Architecture 2013.   R. B. Lee \"Security basics for computer architects \" Synthesis Lectures on Computer Architecture 2013.","DOI":"10.1007\/978-3-031-01742-1"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000086"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2770287.2770300"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168941"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815981"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488867"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333672"}],"event":{"name":"DAC '18: The 55th Annual Design Automation Conference 2018","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco California","acronym":"DAC '18"},"container-title":["Proceedings of the 55th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196007","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3196007","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3196007","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:39:12Z","timestamp":1750210752000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196007"}},"subtitle":["compression architecture for secure low latency, low energy, high endurance NVMs"],"short-title":[],"issued":{"date-parts":[[2018,6,24]]},"references-count":28,"alternative-id":["10.1145\/3195970.3196007","10.1145\/3195970"],"URL":"https:\/\/doi.org\/10.1145\/3195970.3196007","relation":{},"subject":[],"published":{"date-parts":[[2018,6,24]]},"assertion":[{"value":"2018-06-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}