{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:33:09Z","timestamp":1750221189803,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,24]],"date-time":"2018-06-24T00:00:00Z","timestamp":1529798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,24]]},"DOI":"10.1145\/3195970.3196008","type":"proceedings-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T13:54:59Z","timestamp":1529416499000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Closed yet open DRAM"],"prefix":"10.1145","author":[{"given":"Lavanya","family":"Subramanian","sequence":"first","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaushik","family":"Vaidyanathan","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anant","family":"Nori","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sreenivas","family":"Subramoney","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tanay","family":"Karnik","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hong","family":"Wang","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"M. Blackmore \"A quantitative analysis of memory controller page policies \" in Portland State University Dissertation 2010.  M. Blackmore \"A quantitative analysis of memory controller page policies \" in Portland State University Dissertation 2010."},{"key":"e_1_3_2_1_2_1","first-page":"6799241","author":"Kahn O.","year":"2004","unstructured":"O. Kahn and J. Wilcox , \"Method for dynamically adjusting a memory page closing policy,\" U.S. Patent Number 6799241 - 67992B2 , 2004 . O. Kahn and J. Wilcox, \"Method for dynamically adjusting a memory page closing policy,\" U.S. Patent Number 6799241-B2, 2004.","journal-title":"Patent Number"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155624"},{"key":"e_1_3_2_1_4_1","volume-title":"Stride and global history based DRAM page management,\" in JWAC","author":"Khurshid M.","year":"2012","unstructured":"M. Khurshid , \" Stride and global history based DRAM page management,\" in JWAC , 2012 . M. Khurshid et al., \"Stride and global history based DRAM page management,\" in JWAC, 2012."},{"key":"e_1_3_2_1_5_1","volume-title":"A case for subarray-level parallelism (SALP) in DRAM,\" in ISCA","author":"Kim Y.","year":"2012","unstructured":"Y. Kim , \" A case for subarray-level parallelism (SALP) in DRAM,\" in ISCA , 2012 . Y. Kim et al., \"A case for subarray-level parallelism (SALP) in DRAM,\" in ISCA, 2012."},{"key":"e_1_3_2_1_6_1","volume-title":"ATLAS: a scalable and high-performance scheduling algorithm for multiple memory controllers,\" in HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , \" ATLAS: a scalable and high-performance scheduling algorithm for multiple memory controllers,\" in HPCA , 2010 . Y. Kim et al., \"ATLAS: a scalable and high-performance scheduling algorithm for multiple memory controllers,\" in HPCA, 2010."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"R. Kraus \"Analysis and reduction of sense-amplifier offset \" IEEE JSSC vol. 24 Aug 1989.  R. Kraus \"Analysis and reduction of sense-amplifier offset \" IEEE JSSC vol. 24 Aug 1989.","DOI":"10.1109\/4.34088"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522354"},{"key":"e_1_3_2_1_9_1","volume-title":"porous low-k beol, and immersion lithography,\" in IEDM","author":"Narasimha S.","year":"2016","unstructured":"S. Narasimha , \"High performance 45-nm SOI technology with enhanced strain , porous low-k beol, and immersion lithography,\" in IEDM , 2016 . S. Narasimha, \"High performance 45-nm SOI technology with enhanced strain, porous low-k beol, and immersion lithography,\" in IEDM, 2016."},{"key":"e_1_3_2_1_10_1","volume-title":"O et al., \"Row-buffer decoupling: A case for low-latency DRAM microarchitecture,\" in ISCA","author":"S.","year":"2014","unstructured":"S. O et al., \"Row-buffer decoupling: A case for low-latency DRAM microarchitecture,\" in ISCA , 2014 . S. O et al., \"Row-buffer decoupling: A case for low-latency DRAM microarchitecture,\" in ISCA, 2014."},{"key":"e_1_3_2_1_11_1","unstructured":"Rambus \"DRAM power model \" 2010. {Online}. Available: http:\/\/www.rambus.com  Rambus \"DRAM power model \" 2010. {Online}. Available: http:\/\/www.rambus.com"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_13_1","volume-title":"Q-DRAM: Quick-access DRAM with decoupled restoring from row-activation,\" IEEE TC","author":"Shin W.","year":"2016","unstructured":"W. Shin , \" Q-DRAM: Quick-access DRAM with decoupled restoring from row-activation,\" IEEE TC , vol. 65 , July 2016 . W. Shin et al., \"Q-DRAM: Quick-access DRAM with decoupled restoring from row-activation,\" IEEE TC, vol. 65, July 2016."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815972"},{"key":"e_1_3_2_1_15_1","volume-title":"The blacklisting memory scheduler: Achieving high performance and fairness at low cost,\" in ICCD","author":"Subramanian L.","year":"2014","unstructured":"L. Subramanian , \" The blacklisting memory scheduler: Achieving high performance and fairness at low cost,\" in ICCD , 2014 . L. Subramanian et al., \"The blacklisting memory scheduler: Achieving high performance and fairness at low cost,\" in ICCD, 2014."}],"event":{"name":"DAC '18: The 55th Annual Design Automation Conference 2018","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco California","acronym":"DAC '18"},"container-title":["Proceedings of the 55th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196008","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3196008","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:39:12Z","timestamp":1750210752000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196008"}},"subtitle":["achieving low latency and high performance in DRAM memory systems"],"short-title":[],"issued":{"date-parts":[[2018,6,24]]},"references-count":15,"alternative-id":["10.1145\/3195970.3196008","10.1145\/3195970"],"URL":"https:\/\/doi.org\/10.1145\/3195970.3196008","relation":{},"subject":[],"published":{"date-parts":[[2018,6,24]]},"assertion":[{"value":"2018-06-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}