{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:06Z","timestamp":1750221246221,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":32,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,24]],"date-time":"2018-06-24T00:00:00Z","timestamp":1529798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217738"],"award-info":[{"award-number":["CCF-1217738"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,24]]},"DOI":"10.1145\/3195970.3196123","type":"proceedings-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T13:54:59Z","timestamp":1529416499000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["STASH"],"prefix":"10.1145","author":[{"given":"Shivam","family":"Swami","sequence":"first","affiliation":[{"name":"University of Pittsburgh"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joydeep","family":"Rakshit","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488867"},{"key":"e_1_3_2_1_3_1","unstructured":"https:\/\/www.micron.com\/about\/our-innovation\/3d-xpoint-technology.  https:\/\/www.micron.com\/about\/our-innovation\/3d-xpoint-technology."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_3_2_1_6_1","volume-title":"Reliable non-volatile memories: Techniques and measures,\" IEEE Design & Test","author":"Swami S.","year":"2017","unstructured":"S. Swami and K. Mohanram , \" Reliable non-volatile memories: Techniques and measures,\" IEEE Design & Test , 2017 . S. Swami and K. Mohanram, \"Reliable non-volatile memories: Techniques and measures,\" IEEE Design & Test, 2017."},{"key":"e_1_3_2_1_7_1","unstructured":"https:\/\/www.micron.com\/products\/hybrid-memory-cube.  https:\/\/www.micron.com\/products\/hybrid-memory-cube."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000086"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"R. B. Lee \"Security basics for computer architects \" Synthesis Lectures on Computer Architecture 2013.   R. B. Lee \"Security basics for computer architects \" Synthesis Lectures on Computer Architecture 2013.","DOI":"10.1007\/978-3-031-01742-1"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694387"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2538218"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898087"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062205"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080230"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080232"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.44"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.22"},{"volume-title":"Demonstration of reliable triple-level-cell (TLC) phase change memory,\" in IEEE IMW","year":"2016","key":"e_1_3_2_1_18_1","unstructured":"Stanisavljevic , \" Demonstration of reliable triple-level-cell (TLC) phase change memory,\" in IEEE IMW , 2016 . Stanisavljevic et al., \"Demonstration of reliable triple-level-cell (TLC) phase change memory,\" in IEEE IMW, 2016."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_3_2_1_21_1","volume-title":"Dynamic partial power down of memory-side cache in a 2-level memory hierarchy.\" https:\/\/www.google.com\/patents\/US20140304475","author":"Ramanujan R.","year":"2014","unstructured":"R. Ramanujan , \" Dynamic partial power down of memory-side cache in a 2-level memory hierarchy.\" https:\/\/www.google.com\/patents\/US20140304475 , 2014 . R. Ramanujan et al., \"Dynamic partial power down of memory-side cache in a 2-level memory hierarchy.\" https:\/\/www.google.com\/patents\/US20140304475, 2014."},{"key":"e_1_3_2_1_23_1","unstructured":"http:\/\/nvlpubs.nist.gov\/nistpubs\/Legacy\/SP\/nistspecialpublication800-38a.pdf.  http:\/\/nvlpubs.nist.gov\/nistpubs\/Legacy\/SP\/nistspecialpublication800-38a.pdf."},{"key":"e_1_3_2_1_24_1","unstructured":"https:\/\/csrc.nist.gov\/projects\/block-cipher-techniques\/bcm.  https:\/\/csrc.nist.gov\/projects\/block-cipher-techniques\/bcm."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSAC.2008.45"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654117"},{"key":"e_1_3_2_1_27_1","volume-title":"Accelerating application start-up with non-volatile memory in android systems,\" IEEE Micro","author":"Kim H.","year":"2015","unstructured":"H. Kim , \" Accelerating application start-up with non-volatile memory in android systems,\" IEEE Micro , 2015 . H. Kim et al., \"Accelerating application start-up with non-volatile memory in android systems,\" IEEE Micro, 2015."},{"key":"e_1_3_2_1_28_1","volume-title":"Workshop on Near-Data Processing","author":"Eckert Y.","year":"2014","unstructured":"Y. Eckert feasibility of die-stacked processing in memory,\" in Proc . Workshop on Near-Data Processing , 2014 . Y. Eckert et al., \"Thermal feasibility of die-stacked processing in memory,\" in Proc. Workshop on Near-Data Processing, 2014."},{"key":"e_1_3_2_1_29_1","unstructured":"https:\/\/ark.intel.com\/products\/65525\/Intel-Core-i7-3770T-Processor-8M-Cache-up-to-3.70-GHz.  https:\/\/ark.intel.com\/products\/65525\/Intel-Core-i7-3770T-Processor-8M-Cache-up-to-3.70-GHz."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822806"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"}],"event":{"name":"DAC '18: The 55th Annual Design Automation Conference 2018","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco California","acronym":"DAC '18"},"container-title":["Proceedings of the 55th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196123","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3196123","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3196123","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:07:40Z","timestamp":1750212460000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196123"}},"subtitle":["security architecture for smart hybrid memories"],"short-title":[],"issued":{"date-parts":[[2018,6,24]]},"references-count":32,"alternative-id":["10.1145\/3195970.3196123","10.1145\/3195970"],"URL":"https:\/\/doi.org\/10.1145\/3195970.3196123","relation":{},"subject":[],"published":{"date-parts":[[2018,6,24]]},"assertion":[{"value":"2018-06-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}