{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:05Z","timestamp":1750221245822,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,24]],"date-time":"2018-06-24T00:00:00Z","timestamp":1529798400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,24]]},"DOI":"10.1145\/3195970.3196133","type":"proceedings-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T13:54:59Z","timestamp":1529416499000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Ultralow power acoustic feature-scoring using gaussian I-V transistors"],"prefix":"10.1145","author":[{"given":"Amit Ranjan","family":"Trivedi","sequence":"first","affiliation":[{"name":"University of Illinois at Chicago"}]},{"given":"Ahish","family":"Shylendra","sequence":"additional","affiliation":[{"name":"University of Illinois at Chicago"}]}],"member":"320","published-online":{"date-parts":[[2018,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2367818"},{"key":"e_1_3_2_1_2_1","volume-title":"Nanodevice-based novel computing paradigms and the neuromorphic approach,\" in IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Zhao","year":"2012","unstructured":"Zhao et al. , \" Nanodevice-based novel computing paradigms and the neuromorphic approach,\" in IEEE International Symposium on Circuits and Systems (ISCAS) , 2012 . Zhao et al., \"Nanodevice-based novel computing paradigms and the neuromorphic approach,\" in IEEE International Symposium on Circuits and Systems (ISCAS), 2012."},{"key":"e_1_3_2_1_3_1","volume-title":"Speech and Signal Processing (ICASSP)","author":"Swietojanski P.","year":"2013","unstructured":"P. Swietojanski , A. Ghoshal , and S. Renals , \" Revisiting hybrid and gmm-hmm system combination techniques,\" in IEEE International Conference on Acoustics , Speech and Signal Processing (ICASSP) , 2013 . P. Swietojanski, A. Ghoshal, and S. Renals, \"Revisiting hybrid and gmm-hmm system combination techniques,\" in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2013."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Pazhayaveetil D. Chandra P. Franzon \"Flexible low power probability density estimation unit for speech recognition \" In IEEE Symposium on Circuits and Systems 2007.  Pazhayaveetil D. Chandra P. Franzon \"Flexible low power probability density estimation unit for speech recognition \" In IEEE Symposium on Circuits and Systems 2007.","DOI":"10.1109\/ISCAS.2007.378206"},{"key":"e_1_3_2_1_5_1","volume-title":"Gate\/source overlapped heterojunction tunnel fet for non-boolean associative processing with plasticity,\" in International Electron Devices Meeting","author":"Trivedi A. R.","year":"2015","unstructured":"A. R. Trivedi , R. Pandey , H. Liu , S. Datta , and S. Mukhopadhyay , \" Gate\/source overlapped heterojunction tunnel fet for non-boolean associative processing with plasticity,\" in International Electron Devices Meeting , 2015 . A. R. Trivedi, R. Pandey, H. Liu, S. Datta, and S. Mukhopadhyay, \"Gate\/source overlapped heterojunction tunnel fet for non-boolean associative processing with plasticity,\" in International Electron Devices Meeting, 2015."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2388533"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Mohata et al. \"Demonstration of improved heteroepitaxy scaled gate stack and reduced interface states enabling heterojunction tunnel fets with high drive current and high on-off ratio \" in Symposium on VLSI technology 2012.  Mohata et al. \"Demonstration of improved heteroepitaxy scaled gate stack and reduced interface states enabling heterojunction tunnel fets with high drive current and high on-off ratio \" in Symposium on VLSI technology 2012.","DOI":"10.1109\/VLSIT.2012.6242457"},{"key":"e_1_3_2_1_8_1","volume-title":"Hybrid, gate-tunable, van der waals p-n heterojunctions from pentacene and mos2,\" Nano let","author":"Jariwala","year":"2015","unstructured":"Jariwala et al , \" Hybrid, gate-tunable, van der waals p-n heterojunctions from pentacene and mos2,\" Nano let ., 2015 . Jariwala et al, \"Hybrid, gate-tunable, van der waals p-n heterojunctions from pentacene and mos2,\" Nano let., 2015."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488868"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2357777"},{"key":"e_1_3_2_1_11_1","first-page":"231","volume-title":"Ultra-low power electronics with Si\/Ge tunnel FET\" in Proceedings of the conference on Design, Automation, and Test in Europe","author":"Trivedi A. R.","year":"2014","unstructured":"A. R. Trivedi , M. Amir , and S. Mukhopadhyay , \" Ultra-low power electronics with Si\/Ge tunnel FET\" in Proceedings of the conference on Design, Automation, and Test in Europe , p. 231 , 2014 . A. R. Trivedi, M. Amir, and S. Mukhopadhyay, \"Ultra-low power electronics with Si\/Ge tunnel FET\" in Proceedings of the conference on Design, Automation, and Test in Europe, p.231, 2014."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2318046"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1006\/dspr.1999.0361"},{"key":"e_1_3_2_1_14_1","unstructured":"\"Speaker recognition database (open source) \" http:\/\/www.imm.dtu.dk\/~lfen\/Speakerrecognition.htm.  \"Speaker recognition database (open source) \" http:\/\/www.imm.dtu.dk\/~lfen\/Speakerrecognition.htm."},{"key":"e_1_3_2_1_15_1","unstructured":"Fields Guntur. \"Comparative performance analysis of low power full adder design in different logics in 22 nm technology.\"  Fields Guntur. \"Comparative performance analysis of low power full adder design in different logics in 22 nm technology.\""},{"key":"e_1_3_2_1_16_1","unstructured":"http:\/\/www.rroij.com\/peer-reviewed\/design-of-multipliers-using-low-power-highspeed-logic-in-cmos-technologies-43960.html  http:\/\/www.rroij.com\/peer-reviewed\/design-of-multipliers-using-low-power-highspeed-logic-in-cmos-technologies-43960.html"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2623601"},{"key":"e_1_3_2_1_18_1","unstructured":"https:\/\/converterpassion.wordpress.com\/2012\/08\/21\/adc-performance-evolution-walden-figure-of-merit-fom\/  https:\/\/converterpassion.wordpress.com\/2012\/08\/21\/adc-performance-evolution-walden-figure-of-merit-fom\/"}],"event":{"name":"DAC '18: The 55th Annual Design Automation Conference 2018","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE Council on Electronic Design Automation (CEDA)","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco California","acronym":"DAC '18"},"container-title":["Proceedings of the 55th Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196133","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3195970.3196133","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:07:40Z","timestamp":1750212460000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3195970.3196133"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,24]]},"references-count":18,"alternative-id":["10.1145\/3195970.3196133","10.1145\/3195970"],"URL":"https:\/\/doi.org\/10.1145\/3195970.3196133","relation":{},"subject":[],"published":{"date-parts":[[2018,6,24]]},"assertion":[{"value":"2018-06-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}