{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:32:35Z","timestamp":1750221155034,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":47,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,5,14]],"date-time":"2018-05-14T00:00:00Z","timestamp":1526256000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,5,14]]},"DOI":"10.1145\/3204919.3204921","type":"proceedings-article","created":{"date-parts":[[2018,5,2]],"date-time":"2018-05-02T12:21:47Z","timestamp":1525263707000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Nuclear Reactor Simulation on OpenCL FPGA"],"prefix":"10.1145","author":[{"given":"Zheming","family":"Jin","sequence":"first","affiliation":[{"name":"Argonne National Laboratory, Argonne, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hal","family":"Finkel","sequence":"additional","affiliation":[{"name":"Argonne National Laboratory, Argonne, IL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,5,14]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Schatz M.C. Trapnell C. Delcher A.L. and Varshney A. 2007. High-throughput sequence alignment using Graphics Processing Units. BMC bioinformatics 8(1) p.474.  Schatz M.C. Trapnell C. Delcher A.L. and Varshney A. 2007. High-throughput sequence alignment using Graphics Processing Units. BMC bioinformatics 8(1) p.474.","DOI":"10.1186\/1471-2105-8-474"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021749"},{"volume-title":"Computer Vision and Pattern Recognition Workshops, 2008. CVPRW'08. IEEE Computer Society Conference on (pp. 1--6). IEEE.","author":"Garcia V.","key":"e_1_3_2_1_3_1"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554787"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2013.82"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2010.54"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.115"},{"volume-title":"Design Automation Conference (ASP-DAC)","year":"2013","author":"Chen D.","key":"e_1_3_2_1_8_1"},{"first-page":"265","volume-title":"November. TensorFlow: A System for Large-Scale Machine Learning. In OSDI (Vol. 16","author":"Abadi M.","key":"e_1_3_2_1_9_1"},{"volume-title":"Microarchitecture (MICRO), 2016 49th Annual IEEE\/ACM International Symposium on (pp. 1--12)","author":"Sharma H.","key":"e_1_3_2_1_10_1"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.110"},{"key":"e_1_3_2_1_13_1","unstructured":"Intel FPGA SDK for OpenCL Cyclone V SoC Getting Started Guide. Intel (2017)  Intel FPGA SDK for OpenCL Cyclone V SoC Getting Started Guide. Intel (2017)"},{"key":"e_1_3_2_1_14_1","unstructured":"Intel FPGA SDK for OpenCL Stratix V Network Reference Platform Porting Guide. Intel (2017)  Intel FPGA SDK for OpenCL Stratix V Network Reference Platform Porting Guide. Intel (2017)"},{"key":"e_1_3_2_1_15_1","unstructured":"Intel FPGA SDK for OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide. Intel (2017)  Intel FPGA SDK for OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide. Intel (2017)"},{"key":"e_1_3_2_1_16_1","unstructured":"Loring Wirbel: Xilinx SDAccel Whitepaper.Xilinx (2014)  Loring Wirbel: Xilinx SDAccel Whitepaper.Xilinx (2014)"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000005"},{"key":"e_1_3_2_1_18_1","unstructured":"Betz V. Rose J. and Marquardt A. 2012. Architecture and CAD for deep-submicron FPGAs (Vol. 497). Springer Science & Business Media.   Betz V. Rose J. and Marquardt A. 2012. Architecture and CAD for deep-submicron FPGAs (Vol. 497). Springer Science & Business Media."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Koch D. Hannig F. and Ziener D. eds. 2016. FPGAs for Software Programmers. Springer.   Koch D. Hannig F. and Ziener D. eds. 2016. FPGAs for Software Programmers. Springer.","DOI":"10.1007\/978-3-319-26408-0"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"volume-title":"Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on (pp. 531--534)","author":"Czajkowski T.S.","key":"e_1_3_2_1_21_1"},{"key":"e_1_3_2_1_22_1","unstructured":"Intel FPGA SDK for OpenCL Programming Guide. UG-OCL002. 2017.05.08  Intel FPGA SDK for OpenCL Programming Guide. UG-OCL002. 2017.05.08"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.anucene.2013.09.043"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2015.105"},{"key":"e_1_3_2_1_25_1","unstructured":"https:\/\/github.com\/ANL-CESAR\/RSBench  https:\/\/github.com\/ANL-CESAR\/RSBench"},{"key":"e_1_3_2_1_26_1","unstructured":"Intel Arria 10 Device Overview. A10-OVERVIEW. 2017.09.20  Intel Arria 10 Device Overview. A10-OVERVIEW. 2017.09.20"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"Jeffers J. Reinders J. and Sodani A. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann   Jeffers J. Reinders J. and Sodani A. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann","DOI":"10.1016\/B978-0-12-809194-4.00002-8"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435268"},{"volume-title":"International Conference on the Physics of Reactors 2010, PHYSOR 2010.","author":"Xiao S.","key":"e_1_3_2_1_29_1"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"crossref","unstructured":"Xiao S. 2009. Hardware accelerated high performance neutron transport computation based on AGENT methodology (Doctoral dissertation Purdue University).   Xiao S. 2009. Hardware accelerated high performance neutron transport computation based on AGENT methodology (Doctoral dissertation Purdue University).","DOI":"10.1115\/ICONE18-29614"},{"key":"e_1_3_2_1_31_1","first-page":"60526","article-title":"Research on acceleration method of reactor physics based on FPGA platforms. American Nuclear Society, 555 North Kensington Avenue","author":"Li C.","year":"2013","journal-title":"La Grange Park"},{"volume-title":"2010 Symposium on Application Accelerators in High Performance Computing (SAAHPC'10)","author":"Rul S.","key":"e_1_3_2_1_32_1"},{"volume-title":"Proceedings of the conference on Design, Automation & Test in Europe (p. 208)","author":"Morales V.M.","key":"e_1_3_2_1_33_1"},{"volume-title":"Proc. IEEE High Perform. Extreme Comput. Conf.(HPEC) (pp. 1--6).","year":"2013","author":"Settle S.O.","key":"e_1_3_2_1_34_1"},{"key":"e_1_3_2_1_35_1","unstructured":"Verma A. Helal A.E. Krommydas K. and Feng W.C. 2016. Accelerating Workloads on FPGAs via OpenCL: A Case Study with OpenDwarfs. Department of Computer Science Virginia Polytechnic Institute & State University.  Verma A. Helal A.E. Krommydas K. and Feng W.C. 2016. Accelerating Workloads on FPGAs via OpenCL: A Case Study with OpenDwarfs. Department of Computer Science Virginia Polytechnic Institute & State University."},{"volume-title":"ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on (pp. 1--6). IEEE.","author":"Gao S.","key":"e_1_3_2_1_36_1"},{"volume-title":"Computer Design (ICCD), 2016 IEEE 34th International Conference on (pp. 249--256)","author":"Jia Q.","key":"e_1_3_2_1_37_1"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2664666.2664670"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021698"},{"volume-title":"Field-Programmable Technology (FPT), 2014 International Conference on (pp. 12--19)","author":"Inggs G.","key":"e_1_3_2_1_40_1"},{"volume-title":"SC16: International Conference for (pp. 409--420)","author":"Zohouri H.R.","key":"e_1_3_2_1_41_1"},{"volume-title":"Parallel and Distributed Processing Symposium","year":"2016","author":"Lee S.","key":"e_1_3_2_1_42_1"},{"volume-title":"Field Programmable Logic and Applications (FPL), 2017 27th International Conference on (pp. 1--4). IEEE.","author":"Luo Y.","key":"e_1_3_2_1_43_1"},{"volume-title":"European Conference on Parallel Processing (pp. 664--675)","author":"Jin Z.","key":"e_1_3_2_1_44_1"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2688500.2688501"},{"volume-title":"Field Programmable Logic and Applications (FPL), 2015 25th International Conference on (pp. 1--8). IEEE.","author":"Wang Z.","key":"e_1_3_2_1_46_1"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847343"}],"event":{"name":"IWOCL '18: International Workshop on OpenCL","sponsor":["Huawei Technologies Co. Ltd. Huawei Technologies Co. Ltd.","Khronos Khronos Group","Xilinx Xilinx Inc.","Codeplay Codeplay Software Ltd.","Intel Intel","The University of Bristol The University of Bristol"],"location":"Oxford United Kingdom","acronym":"IWOCL '18"},"container-title":["Proceedings of the International Workshop on OpenCL"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3204919.3204921","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3204919.3204921","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:31Z","timestamp":1750208911000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3204919.3204921"}},"subtitle":["a Case Study of RSBench"],"short-title":[],"issued":{"date-parts":[[2018,5,14]]},"references-count":47,"alternative-id":["10.1145\/3204919.3204921","10.1145\/3204919"],"URL":"https:\/\/doi.org\/10.1145\/3204919.3204921","relation":{},"subject":[],"published":{"date-parts":[[2018,5,14]]},"assertion":[{"value":"2018-05-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}