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Storage"],"published-print":{"date-parts":[[2018,8,31]]},"abstract":"<jats:p>\n            Phase Change Memory (PCM) has drawn great attention as a main memory due to its attractive characteristics such as non-volatility, byte-addressability, and in-place update. However, since the capacity of PCM is not fully mature yet,\n            <jats:italic>hybrid memory architecture<\/jats:italic>\n            that consists of DRAM and PCM has been suggested as a main memory. In addition, page replacement algorithm based on\n            <jats:italic>hybrid memory architecture<\/jats:italic>\n            is actively being studied, because existing page replacement algorithms cannot be used on\n            <jats:italic>hybrid memory architecture<\/jats:italic>\n            in that they do not consider the two weaknesses of PCM: high write latency and low endurance. In this article, to mitigate the above hardware limitations of PCM, we revisit the page cache layer for the\n            <jats:italic>hybrid memory architecture<\/jats:italic>\n            and propose a novel page replacement algorithm, called M-CLOCK, to improve the performance of\n            <jats:italic>hybrid memory architecture<\/jats:italic>\n            and the lifespan of PCM. In particular, M-CLOCK aims to reduce the number of PCM writes that negatively affect the performance of\n            <jats:italic>hybrid memory architecture<\/jats:italic>\n            . Experimental results clearly show that M-CLOCK outperforms the state-of-the-art page replacement algorithms in terms of the number of PCM writes and effective memory access time by up to 98% and 9.4 times, respectively.\n          <\/jats:p>","DOI":"10.1145\/3216730","type":"journal-article","created":{"date-parts":[[2018,10,3]],"date-time":"2018-10-03T11:57:58Z","timestamp":1538567878000},"page":"1-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["M-CLOCK"],"prefix":"10.1145","volume":"14","author":[{"given":"Minho","family":"Lee","sequence":"first","affiliation":[{"name":"Sungkyunkwan University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dong Hyun","family":"Kang","sequence":"additional","affiliation":[{"name":"Sungkyunkwan University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Young Ik","family":"Eom","sequence":"additional","affiliation":[{"name":"Sungkyunkwan University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,10,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968478.2968497"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201911)","author":"Chung Hoeju","year":"2011","unstructured":"Hoeju Chung , Byung Hoon Jeong , and Byungjun Min . 2011 . A58nm 1.8V 1Gb PRAM with 6.4MB\/s program BW . In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201911) . IEEE, 500--502. Hoeju Chung, Byung Hoon Jeong, and Byungjun Min. 2011. A58nm 1.8V 1Gb PRAM with 6.4MB\/s program BW. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201911). IEEE, 500--502."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2901318.2901344"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2009.5090604"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1871147"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the USENIX Annual Technical Conference (ATC\u201905)","author":"Jiang Song","year":"2005","unstructured":"Song Jiang , Feng Chen , and Xiaodong Zhang . 2005 . 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