{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:33:51Z","timestamp":1750221231398,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,7,23]],"date-time":"2018-07-23T00:00:00Z","timestamp":1532304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CAEEER-1253024, CNS-1117425, CFF-1318826,CNS1421022,CNS-1421068"],"award-info":[{"award-number":["CAEEER-1253024, CNS-1117425, CFF-1318826,CNS1421022,CNS-1421068"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,7,23]]},"DOI":"10.1145\/3218603.3218644","type":"proceedings-article","created":{"date-parts":[[2019,2,19]],"date-time":"2019-02-19T20:59:18Z","timestamp":1550609958000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["ACE-GPU"],"prefix":"10.1145","author":[{"given":"Tahmoures","family":"Shabanian","sequence":"first","affiliation":[{"name":"USU BRIDGE LAB, Electrical and Computer Engineering Department, Utah State University, Logan, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aatreyi","family":"Bal","sequence":"additional","affiliation":[{"name":"USU BRIDGE LAB, Electrical and Computer Engineering Department, Utah State University, Logan, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Prabal","family":"Basu","sequence":"additional","affiliation":[{"name":"USU BRIDGE LAB, Electrical and Computer Engineering Department, Utah State University, Logan, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koushik","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"USU BRIDGE LAB, Electrical and Computer Engineering Department, Utah State University, Logan, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanghamitra","family":"Roy","sequence":"additional","affiliation":[{"name":"USU BRIDGE LAB, Electrical and Computer Engineering Department, Utah State University, Logan, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,7,23]]},"reference":[{"unstructured":"2015. MIAOW GPU - An open source RTL implementation of a GPGPU. http:\/\/miaowgpu.org.  2015. MIAOW GPU - An open source RTL implementation of a GPGPU. http:\/\/miaowgpu.org.","key":"e_1_3_2_1_1_1"},{"unstructured":"2016. AMD Accelerated Parallel Processing (APP) Software Development Kit. http:\/\/developer.amd.com\/sdks\/amdappsdk\/  2016. AMD Accelerated Parallel Processing (APP) Software Development Kit. http:\/\/developer.amd.com\/sdks\/amdappsdk\/","key":"e_1_3_2_1_2_1"},{"volume-title":"Proc. of DATE. 1--6.","year":"2014","author":"Aguilera Paula","key":"e_1_3_2_1_3_1"},{"unstructured":"Aatreyi Bal Shamik Saha Sanghamitra Roy and Koushik Chakraborty. 2017. Revamping Timing Error Resilience To Tackle Choke Points at NTC systems. 1020--1025.   Aatreyi Bal Shamik Saha Sanghamitra Roy and Koushik Chakraborty. 2017. Revamping Timing Error Resilience To Tackle Choke Points at NTC systems. 1020--1025.","key":"e_1_3_2_1_4_1"},{"doi-asserted-by":"crossref","unstructured":"Prabal Basu Hu Chen Shamik Saha Koushik Chakraborty and Sanghamitra Roy. 2016. SwiftGPU: Fostering Energy Efficiency in a Near-Threshold GPU Through Tactical Performance Boost.  Prabal Basu Hu Chen Shamik Saha Koushik Chakraborty and Sanghamitra Roy. 2016. SwiftGPU: Fostering Energy Efficiency in a Near-Threshold GPU Through Tactical Performance Boost.","key":"e_1_3_2_1_5_1","DOI":"10.1145\/2897937.2898100"},{"doi-asserted-by":"crossref","unstructured":"Leland Chang David J. Frank Robert K. Montoye Steven J. Koester Brian L. Ji Paul W. Coteus Robert H. Dennard and Wilfried Haensch. 2010. Practical Strategies for Power-Efficient Computing Technologies. 98 2 (2010) 215--236.  Leland Chang David J. Frank Robert K. Montoye Steven J. Koester Brian L. Ji Paul W. Coteus Robert H. Dennard and Wilfried Haensch. 2010. Practical Strategies for Power-Efficient Computing Technologies. 98 2 (2010) 215--236.","key":"e_1_3_2_1_6_1","DOI":"10.1109\/JPROC.2009.2035451"},{"unstructured":"Design Compiler RTL User and Modeling Guide. 2001. Synopsys. Inc. see http:\/\/www. synopsys. com (2001).  Design Compiler RTL User and Modeling Guide. 2001. Synopsys. Inc. see http:\/\/www. synopsys. com (2001).","key":"e_1_3_2_1_7_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.5555\/2840819.2840842"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/JPROC.2009.2034764"},{"volume-title":"Proc. of MICRO. 7--18","author":"Ernst Dan","key":"e_1_3_2_1_10_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1109\/MM.2013.71"},{"doi-asserted-by":"crossref","unstructured":"Ulya R. Karpuzcu Krishna B. Kolluru Nam Sung Kim and Josep Torrellas. 2012. VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. 1--11.   Ulya R. Karpuzcu Krishna B. Kolluru Nam Sung Kim and Josep Torrellas. 2012. VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. 1--11.","key":"e_1_3_2_1_12_1","DOI":"10.1109\/DSN.2012.6263951"},{"doi-asserted-by":"crossref","unstructured":"S Karen Khatamifard Michael Resch Nam Sung Kim and Ulya R Karpuzcu. 2016. VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches. 654--661.  S Karen Khatamifard Michael Resch Nam Sung Kim and Ulya R Karpuzcu. 2016. VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches. 654--661.","key":"e_1_3_2_1_13_1","DOI":"10.1109\/ICCD.2016.7753353"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1145\/2628071.2628107"},{"doi-asserted-by":"crossref","unstructured":"Jan Lucas Sohan Lal Michael Andersch Mauricio Alvarez-Mesa and Ben Juurlink. 2013. How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator. In ISPASS.  Jan Lucas Sohan Lal Michael Andersch Mauricio Alvarez-Mesa and Ben Juurlink. 2013. How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator. In ISPASS.","key":"e_1_3_2_1_15_1","DOI":"10.1109\/ISPASS.2013.6557150"},{"unstructured":"NanGate. {n. d.}. http:\/\/www.nangate.com\/?page_id=2328.  NanGate. {n. d.}. http:\/\/www.nangate.com\/?page_id=2328.","key":"e_1_3_2_1_16_1"},{"volume-title":"Proc. of DATE. 1695--1700","author":"Rahimi Abbas","key":"e_1_3_2_1_17_1"},{"doi-asserted-by":"crossref","unstructured":"S.R. Sarangi B. Greskamp R. Teodorescu J. Nakano A. Tiwari and J. Torrellas. 2008. VARIUS:A Model of Process Variation and Resulting Timing Errors for Microarchitects. 21 (2008) 3 -13.  S.R. Sarangi B. Greskamp R. Teodorescu J. Nakano A. Tiwari and J. Torrellas. 2008. VARIUS:A Model of Process Variation and Resulting Timing Errors for Microarchitects. 21 (2008) 3 -13.","key":"e_1_3_2_1_18_1","DOI":"10.1109\/TSM.2007.913186"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1145\/2228360.2228536"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.1145\/2370816.2370865"}],"event":{"sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS"],"acronym":"ISLPED '18","name":"ISLPED '18: International Symposium on Low Power Electronics and Design","location":"Seattle WA USA"},"container-title":["Proceedings of the International Symposium on Low Power Electronics and Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3218603.3218644","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3218603.3218644","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3218603.3218644","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:07:04Z","timestamp":1750212424000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3218603.3218644"}},"subtitle":["Tackling Choke Point Induced Performance Bottlenecks in a Near-Threshold Computing GPU"],"short-title":[],"issued":{"date-parts":[[2018,7,23]]},"references-count":20,"alternative-id":["10.1145\/3218603.3218644","10.1145\/3218603"],"URL":"https:\/\/doi.org\/10.1145\/3218603.3218644","relation":{},"subject":[],"published":{"date-parts":[[2018,7,23]]},"assertion":[{"value":"2018-07-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}