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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2018,9,30]]},"abstract":"<jats:p>Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.<\/jats:p>","DOI":"10.1145\/3223046","type":"journal-article","created":{"date-parts":[[2018,8,23]],"date-time":"2018-08-23T11:48:27Z","timestamp":1535024907000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":33,"title":["Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip"],"prefix":"10.1145","volume":"23","author":[{"given":"Dongjin","family":"Lee","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sourav","family":"Das","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Janardhan Rao","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, Washington"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Duke University, Hudson Hall, Durham, NC"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,8,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2223593"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE International Interconnect Technology Conference. 373--376","author":"Batude P.","unstructured":"P. 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