{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T16:57:14Z","timestamp":1781283434571,"version":"3.54.1"},"reference-count":162,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2018,12,21]],"date-time":"2018-12-21T00:00:00Z","timestamp":1545350400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100011030","name":"U.S. Department of Energy","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100011030","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1212962,1320531"],"award-info":[{"award-number":["1212962,1320531"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Meas. Anal. Comput. Syst."],"published-print":{"date-parts":[[2018,12,21]]},"abstract":"<jats:p>Main memory (DRAM) consumes as much as half of the total system power in a computer today, due to the increasing demand for memory capacity and bandwidth. There is a growing need to understand and analyze DRAM power consumption, which can be used to research new DRAM architectures and systems that consume less power. A major obstacle against such research is the lack of detailed and accurate information on the power consumption behavior of modern DRAM devices. Researchers have long relied on DRAM power models that are predominantly based off of a set of standardized current measurements provided by DRAM vendors, called IDD values. Unfortunately, we find that state-of-the-art DRAM power models are often highly inaccurate, as these models do not reflect the actual power consumed by real DRAM devices. To build an accurate model and provide insights into DRAM power consumption, we perform the first comprehensive experimental characterization of the power consumed by modern real-world DRAM modules. Our extensive characterization of 50 DDR3L DRAM modules from three major vendors yields four key new observations about DRAM power consumption that prior models cannot capture: (1) across all IDD values that we measure, the current consumed by real DRAM modules varies significantly from the current specified by the vendors; (2) DRAM power consumption strongly depends on the data value that is read or written; (3) there is significant structural variation, where the same banks and rows across multiple DRAM modules from the same model consume more power than other banks or rows; and (4) over successive process technology generations, DRAM power consumption has not decreased by as much as vendor specifications have indicated. Because state-of-the-art DRAM power models do not account for any of these four key characteristics, they are highly inaccurate compared to the actual, measured power consumption of 50 real DDR3L modules. Based on our detailed analysis and characterization data, we develop the Variation-Aware model of Memory Power Informed by Real Experiments (VAMPIRE). VAMPIRE is a new, accurate power consumption model for DRAM that takes into account (1) module-to-module and intra-module variations, and (2) power consumption variation due to data value dependency. We show that VAMPIRE has a mean absolute percentage error of only 6.8% compared to actual measured DRAM power. VAMPIRE enables a wide range of studies that were not possible using prior DRAM power models. As an example, we use VAMPIRE to evaluate the energy efficiency of three different encodings that can be used to store data in DRAM. We find that a new power-aware data encoding mechanism can reduce total DRAM energy consumption by an average of 12.2%, across a wide range of applications. We have open-sourced both VAMPIRE and our extensive raw data collected during our experimental characterization.<\/jats:p>","DOI":"10.1145\/3224419","type":"journal-article","created":{"date-parts":[[2018,12,26]],"date-time":"2018-12-26T12:39:28Z","timestamp":1545827968000},"page":"1-41","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":54,"title":["What Your DRAM Power Models Are Not Telling You"],"prefix":"10.1145","volume":"2","author":[{"given":"Saugata","family":"Ghose","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Abdullah Giray","family":"Yaglik\u00e7i","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich \/ Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Raghav","family":"Gupta","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donghyuk","family":"Lee","sequence":"additional","affiliation":[{"name":"NVIDIA, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kais","family":"Kudrolli","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"William X.","family":"Liu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hasan","family":"Hassan","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kevin K.","family":"Chang","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Niladrish","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"NVIDIA, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Aditya","family":"Agrawal","sequence":"additional","affiliation":[{"name":"NVIDIA, Santa Clara, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mike","family":"O'Connor","sequence":"additional","affiliation":[{"name":"NVIDIA \/ University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich \/ Carnegie Mellon University, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,12,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658649"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835978"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1028176.1006719"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840930"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2367736.2367742"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956579"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/2648668.2648720"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750408"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416646"},{"key":"e_1_2_1_11_1","volume-title":"CAN","volume":"39","author":"Binkert N.","year":"2011"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540729"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339657"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.61"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.49"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056062"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378623"},{"key":"e_1_2_1_18_1","author":"Cai Y.","year":"2013","journal-title":"tel Technol. J."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-13-0599-3_9"},{"key":"e_1_2_1_21_1","volume-title":"DATE","author":"Cai Y.","year":"2012"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485597"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657034"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2637364.2591994"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/2616606.2616820"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2011.17"},{"key":"e_1_2_1_27_1","unstructured":"K. Chandrasekar C. Weis Y. Li S. Goossens M. Jung O. Naji B. Akesson N. Wehn and K. Goossens \u201cDRAMPower: Open-Source DRAM Power & Energy Estimation Tool \u201d http:\/\/www.drampower.info.  K. Chandrasekar C. Weis Y. Li S. Goossens M. Jung O. Naji B. Akesson N. Wehn and K. Goossens \u201cDRAMPower: Open-Source DRAM Power & Energy Estimation Tool \u201d http:\/\/www.drampower.info."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835946"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078590"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.58"},{"key":"e_1_2_1_34_1","volume-title":"DATE","author":"Chen K.","year":"2012"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"e_1_2_1_36_1","volume-title":"MEMCON","author":"Choi J. Y.","year":"2013"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.43"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1998582.1998590"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513973"},{"key":"e_1_2_1_40_1","volume-title":"HPCA","author":"Luz V. De La","year":"2001"},{"key":"e_1_2_1_41_1","volume-title":"DAC","author":"Luz V. De La","year":"2002"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1961296.1950392"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.21"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250699"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542288"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1069978"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383118"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_2_1_51_1","volume-title":"Theoria Motus Corporum Coelestium in Sectionibus Conicis Solem Ambientium .hskip 1em plus 0.5em minus 0.4emrelax F. Perthes et I. H. Besser","author":"Gauss C. F.","year":"1809"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446096"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.62"},{"key":"e_1_2_1_54_1","unstructured":"Hewlett Packard Enterprise \u201cCACTI 7.0 \u201d https:\/\/github.com\/HewlettPackard\/cacti.  Hewlett Packard Enterprise \u201cCACTI 7.0 \u201d https:\/\/github.com\/HewlettPackard\/cacti."},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015395"},{"key":"e_1_2_1_56_1","volume-title":"The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines .hskip 1em plus 0.5em minus 0.4emrelax Morgan & Claypool","author":"Holzle U.","year":"2009"},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703348"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.2150989"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.5931"},{"key":"e_1_2_1_60_1","volume-title":"JESD79--3F: DDR3 SDRAM Standard","author":"Solid State Technology Assn JEDEC","year":"2012"},{"key":"e_1_2_1_61_1","volume-title":"DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866","author":"Solid State Technology Assn JEDEC","year":"2013"},{"key":"e_1_2_1_62_1","volume-title":"204-Pin DDR3 SDRAM Unbuffered SO-DIMM Design Specification","author":"Solid State Technology Assn JEDEC","year":"2014"},{"key":"e_1_2_1_63_1","volume-title":"JESD209--3C: Low Power Double Data Rate 3 SDRAM (LPDDR3) Standard","author":"Solid State Technology Assn JEDEC","year":"2015"},{"key":"e_1_2_1_64_1","volume-title":"JESD209--4B: Low Power Double Data Rate 4 (LPDDR4) Standard","author":"Solid State Technology Assn JEDEC","year":"2017"},{"key":"e_1_2_1_65_1","volume-title":"PATMOS","author":"Jung M.","year":"2016"},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2705144"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023838"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.5555\/603095.603136"},{"key":"e_1_2_1_69_1","volume-title":"DATE","author":"Kandemir M.","year":"2007"},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155624"},{"key":"e_1_2_1_71_1","doi-asserted-by":"crossref","DOI":"10.1109\/9780470544426","volume-title":"DRAM Circuit Design: Fundamental and High-Speed Topics .hskip 1em plus 0.5em minus 0.4emrelax Wiley-IEEE Press","author":"Keeth B.","year":"2007"},{"key":"e_1_2_1_72_1","unstructured":"Keysight Technologies Inc. 34134A AC\/DC DMM Current Probe: User's Guide https:\/\/literature.cdn.keysight.com\/litweb\/pdf\/34134--90001.pdf 2009.  Keysight Technologies Inc. 34134A AC\/DC DMM Current Probe: User's Guide https:\/\/literature.cdn.keysight.com\/litweb\/pdf\/34134--90001.pdf 2009."},{"key":"e_1_2_1_73_1","unstructured":"Keysight Technologies Inc. Keysight Truevolt Series Digital Multimeters: Operating and Service Guide https:\/\/literature.cdn.keysight.com\/litweb\/pdf\/34460--90901.pdf 2017.  Keysight Technologies Inc. Keysight Truevolt Series Digital Multimeters: Operating and Service Guide https:\/\/literature.cdn.keysight.com\/litweb\/pdf\/34460--90901.pdf 2017."},{"key":"e_1_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/2637364.2592000"},{"key":"e_1_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"e_1_2_1_76_1","volume-title":"CAL","author":"Khan S.","year":"2016"},{"key":"e_1_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123945"},{"key":"e_1_2_1_78_1","volume-title":"WWC","author":"Kim H. S.","year":"2000"},{"key":"e_1_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00026"},{"key":"e_1_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"e_1_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379007"},{"key":"e_1_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669155"},{"key":"e_1_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"e_1_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078533"},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522354"},{"key":"e_1_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"e_1_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"key":"e_1_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250880"},{"key":"e_1_2_1_94_1","volume-title":"Didot","author":"Legendre A.-M.","year":"1805"},{"key":"e_1_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378619"},{"key":"e_1_2_1_97_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485928"},{"key":"e_1_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337161"},{"key":"e_1_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1145\/1961296.1950391"},{"key":"e_1_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00050"},{"key":"e_1_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.1145\/3219617.3219659"},{"key":"e_1_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996596"},{"key":"e_1_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337164"},{"key":"e_1_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.21"},{"key":"e_1_2_1_106_1","volume-title":"DATE","author":"Mathew D. M.","year":"2018"},{"key":"e_1_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1145\/3023973.3023978"},{"key":"e_1_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.57"},{"key":"e_1_2_1_109_1","unstructured":"MFactors \u201cJET-5467A Product Page \u201d http:\/\/www.mfactors.com\/jet-5467a-ddr3-sodimm-extender-with-current-sensing\/.  MFactors \u201cJET-5467A Product Page \u201d http:\/\/www.mfactors.com\/jet-5467a-ddr3-sodimm-extender-with-current-sensing\/."},{"key":"e_1_2_1_110_1","unstructured":"Micron Technology Inc. \u201cDDR3 Point-to-Point Design Support \u201d Technical Note TN-41--13 2013.  Micron Technology Inc. \u201cDDR3 Point-to-Point Design Support \u201d Technical Note TN-41--13 2013."},{"key":"e_1_2_1_111_1","unstructured":"Micron Technology Inc. \u201cCalculating Memory System Power for DDR3 \u201d Technical Note TN-41-01 2015.  Micron Technology Inc. \u201cCalculating Memory System Power for DDR3 \u201d Technical Note TN-41-01 2015."},{"key":"e_1_2_1_112_1","unstructured":"Micron Technology Inc. \u201cDDR4 Point-to-Point Design Guide \u201d Technical Note TN-40--40 2018.  Micron Technology Inc. \u201cDDR4 Point-to-Point Design Guide \u201d Technical Note TN-40--40 2018."},{"key":"e_1_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485927"},{"key":"e_1_2_1_114_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1996.553853"},{"key":"e_1_2_1_115_1","volume-title":"DATE","author":"Mutlu O.","year":"2017"},{"key":"e_1_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_2_1_117_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"e_1_2_1_118_1","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280792"},{"key":"e_1_2_1_119_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.43"},{"key":"e_1_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_2_1_121_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080242"},{"key":"e_1_2_1_122_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750404"},{"key":"e_1_2_1_123_1","volume-title":"Proc. Royal Soc","author":"Pearson K.","year":"1895"},{"key":"e_1_2_1_124_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446064"},{"key":"e_1_2_1_125_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056021"},{"key":"e_1_2_1_126_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540724"},{"key":"e_1_2_1_127_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_2_1_128_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"e_1_2_1_129_1","unstructured":"Rambus Inc. \u201cRDRAM Memory Architecture \u201d https:\/\/www.rambus.com\/memory-and-interfaces\/rdram-memory-architecture\/.  Rambus Inc. \u201cRDRAM Memory Architecture \u201d https:\/\/www.rambus.com\/memory-and-interfaces\/rdram-memory-architecture\/."},{"key":"e_1_2_1_130_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"e_1_2_1_131_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_2_1_132_1","volume-title":"Characterization Results of Modern DRAM Devices Under Reduced-Voltage Operation -- GitHub Repository","author":"SAFARI Research Group"},{"key":"e_1_2_1_133_1","volume-title":"Ramulator: A DRAM Simulator -- GitHub Repository","author":"SAFARI Research Group"},{"key":"e_1_2_1_134_1","volume-title":"SoftMC -- GitHub Repository","author":"SAFARI Research Group"},{"key":"e_1_2_1_135_1","volume-title":"VAMPIRE -- GitHub Repository","author":"SAFARI Research Group"},{"key":"e_1_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1145\/2492101.1555372"},{"key":"e_1_2_1_137_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_2_1_139_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_2_1_140_1","volume-title":"Advances in Computers","volume":"106","author":"Seshadri V.","year":"2017"},{"key":"e_1_2_1_141_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835956"},{"key":"e_1_2_1_142_1","doi-asserted-by":"publisher","DOI":"10.1145\/2775054.2694348"},{"key":"e_1_2_1_143_1","volume-title":"SC","author":"Sridharan V.","year":"2012"},{"key":"e_1_2_1_144_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"},{"key":"e_1_2_1_145_1","doi-asserted-by":"publisher","DOI":"10.5555\/795679.797415"},{"key":"e_1_2_1_146_1","volume-title":"SPEC CPU2006 Benchmarks","author":"Standard Performance Evaluation Corp.","year":"2006"},{"key":"e_1_2_1_147_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815972"},{"key":"e_1_2_1_148_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.102"},{"key":"e_1_2_1_149_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735970.1736045"},{"key":"e_1_2_1_150_1","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.2009.5433222"},{"key":"e_1_2_1_151_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"e_1_2_1_152_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598122"},{"key":"e_1_2_1_153_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750399"},{"key":"e_1_2_1_154_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"e_1_2_1_155_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835958"},{"key":"e_1_2_1_156_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380850"},{"key":"e_1_2_1_157_1","volume-title":"HPCA","author":"Ware M.","year":"2010"},{"key":"e_1_2_1_158_1","volume-title":"USENIX ATC","author":"Wilson P. R.","year":"1999"},{"key":"e_1_2_1_159_1","unstructured":"Xilinx Inc. \u201cVirtex-6 FPGA Family \u201d https:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/virtex-6.html.  Xilinx Inc. \u201cVirtex-6 FPGA Family \u201d https:\/\/www.xilinx.com\/products\/silicon-devices\/fpga\/virtex-6.html."},{"key":"e_1_2_1_160_1","unstructured":"Xilinx Inc. \u201cML605 Hardware User Guide \u201d https:\/\/www.xilinx.com\/support\/documentation\/boards_and_kits\/ug534.pdf 2012.  Xilinx Inc. \u201cML605 Hardware User Guide \u201d https:\/\/www.xilinx.com\/support\/documentation\/boards_and_kits\/ug534.pdf 2012."},{"key":"e_1_2_1_161_1","unstructured":"Xilinx Inc. \u201cMIG 7 Series and Virtex-6 DDR2\/DDR3 Solution Center - Design Assistant - Memory Controller Efficiency and Possible Improvements \u201d https:\/\/www.xilinx.com\/support\/answers\/36719.html 2017.  Xilinx Inc. \u201cMIG 7 Series and Virtex-6 DDR2\/DDR3 Solution Center - Design Assistant - Memory Controller Efficiency and Possible Improvements \u201d https:\/\/www.xilinx.com\/support\/answers\/36719.html 2017."},{"key":"e_1_2_1_162_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360154"},{"key":"e_1_2_1_163_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337163"},{"key":"e_1_2_1_164_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000100"},{"key":"e_1_2_1_165_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665724"},{"key":"e_1_2_1_166_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"e_1_2_1_167_1","volume-title":"U.S. Patent No. 5,630,096","author":"Zuravleff W.","year":"1997"}],"container-title":["Proceedings of the ACM on Measurement and Analysis of Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3224419","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3224419","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3224419","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:39:06Z","timestamp":1750210746000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3224419"}},"subtitle":["Lessons from a Detailed Experimental Study"],"short-title":[],"issued":{"date-parts":[[2018,12,21]]},"references-count":162,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,12,21]]}},"alternative-id":["10.1145\/3224419"],"URL":"https:\/\/doi.org\/10.1145\/3224419","relation":{},"ISSN":["2476-1249"],"issn-type":[{"value":"2476-1249","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,12,21]]},"assertion":[{"value":"2018-12-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}