{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T16:47:59Z","timestamp":1775494079823,"version":"3.50.1"},"reference-count":44,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2018,7,31]],"date-time":"2018-07-31T00:00:00Z","timestamp":1532995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2018,7,31]]},"abstract":"<jats:p>Many fabrication-less design houses are outsourcing their designs to third-party foundries for fabrication to lower cost. This IC development process, however, raises serious security concerns on Hardware Trojans (HTs). Many design-for-trust techniques have been proposed to detect HTs through observing erroneous output or abnormal side-channel characteristics. Side-channel characteristics such as path delay have been widely used for HT detection and functionality verification, as the changes of the characteristics of the host circuit incurred by the inserted HT can be identified through proper methods.<\/jats:p>\n          <jats:p>In this article, for the first time, we propose a two-phase technique, which uses the order of the path delay in path pairs to detect HTs. In the design phase, a full-cover path set that covers all the nets of the design is generated; meanwhile, in the set, the relative order of paths in path pairs is determined according to their delay. The order of the paths in path pairs serves as the fingerprint of the design. In the test phase, the actual delay of the paths in the full-cover set is extracted from the fabricated circuits, and the order of paths in path pairs is compared with the fingerprint generated in the design phase. A mismatch between them indicates the existence of HTs. Both process variations and measurement noise are taken into consideration. The efficiency and accuracy of the proposed technique are confirmed by a series of experiments, including the examination of both violated path pairs incurred by HTs and their false alarm rate.<\/jats:p>","DOI":"10.1145\/3229050","type":"journal-article","created":{"date-parts":[[2018,10,24]],"date-time":"2018-10-24T11:57:18Z","timestamp":1540382238000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Hardware Trojan Detection Using the Order of Path Delay"],"prefix":"10.1145","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7208-1204","authenticated-orcid":false,"given":"Xiaotong","family":"Cui","sequence":"first","affiliation":[{"name":"Chongqing University, Chongqing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elnaz","family":"Koopahi","sequence":"additional","affiliation":[{"name":"University of Isfahan, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6127-8469","authenticated-orcid":false,"given":"Kaijie","family":"Wu","sequence":"additional","affiliation":[{"name":"New York University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[{"name":"New York University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,10,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233541"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5224960"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the International Workshop on Tau Lepton Physics (TAU\u201997)","volume":"97","author":"Berkelaar M. R. C. M.","year":"1997","unstructured":"M. R. C. M. Berkelaar . 1997 . Statistical delay calculation, a linear time method . In Proceedings of the International Workshop on Tau Lepton Physics (TAU\u201997) , Vol. 97 . 4--5. M. R. C. M. Berkelaar. 1997. Statistical delay calculation, a linear time method. In Proceedings of the International Workshop on Tau Lepton Physics (TAU\u201997), Vol. 97. 4--5."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2334493"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2014.2360432"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 1265--1270","author":"Cha Byeongju","unstructured":"Byeongju Cha and Sandeep K. Gupta . 2013. Trojan detection via delay measurements: A new approach to select paths and vectors to maximize effectiveness and minimize cost . In Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 1265--1270 . Byeongju Cha and Sandeep K. Gupta. 2013. Trojan detection via delay measurements: A new approach to select paths and vectors to maximize effectiveness and minimize cost. In Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 1265--1270."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559048"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593150"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1360\/crad20050121"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009952"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD\u201905)","author":"Doh Ji-Seong","year":"2005","unstructured":"Ji-Seong Doh , Dae-Wook Kim , Sang-Hoon Lee , Jong-Bae Lee , Young-Kwan Park , Moon-Hyun Yoo , and Jeong-Taek Kong . 2005 . A unified statistical model for inter-die and intra-die process variation . In Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD\u201905) . IEEE, 131--134. Ji-Seong Doh, Dae-Wook Kim, Sang-Hoon Lee, Jong-Bae Lee, Young-Kwan Park, Moon-Hyun Yoo, and Jeong-Taek Kong. 2005. A unified statistical model for inter-die and intra-die process variation. In Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD\u201905). IEEE, 131--134."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140254"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429392"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967061"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE International Test Conference (ITC\u201906)","author":"Iyengar Vikram","unstructured":"Vikram Iyengar , Toshihiko Yokota , Kazuhiro Yamada , Theo Anemikos , Bob Bassett , Mike Degregorio , Rudy Farmer , Gary Grise , Mark Johnson , Dave Milton et al. 2006. At-speed structural test for high-performance ASICs . In Proceedings of the IEEE International Test Conference (ITC\u201906) . IEEE, 1--10. Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton et al. 2006. At-speed structural test for high-performance ASICs. In Proceedings of the IEEE International Test Conference (ITC\u201906). IEEE, 1--10."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559049"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.299"},{"key":"e_1_2_1_18_1","volume-title":"Advanced FPGA Design: Architecture, Implementation, and Optimization","author":"Kilts Steve","unstructured":"Steve Kilts . 2007. Advanced FPGA Design: Architecture, Implementation, and Optimization . IEEE. Steve Kilts. 2007. Advanced FPGA Design: Architecture, Implementation, and Optimization. IEEE."},{"key":"e_1_2_1_19_1","volume-title":"Combinatorial Optimization: Theory and Algorithms","author":"Korte Bernhard","year":"2008","unstructured":"Bernhard Korte and Jens Vygen . 2008 . Combinatorial Optimization: Theory and Algorithms . Springer-Verlag , Heidelberg . Bernhard Korte and Jens Vygen. 2008. Combinatorial Optimization: Theory and Algorithms. Springer-Verlag, Heidelberg."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224324"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601924"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593147"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2871167"},{"key":"e_1_2_1_24_1","volume-title":"Low noise signal conditioning for sensor-based circuits. System 1","author":"Moghimi Reza","year":"2010","unstructured":"Reza Moghimi . 2010. Low noise signal conditioning for sensor-based circuits. System 1 ( 2010 ), 2 pages. Reza Moghimi. 2010. Low noise signal conditioning for sensor-based circuits. System 1 (2010), 2 pages."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.protcy.2014.10.197"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.01.003"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5224966"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD\u201907)","author":"Ravindra J. V. R.","unstructured":"J. V. R. Ravindra and M. B. Srinivas . 2007. A statistical model for estimating the effect of process variations on delay and slew metrics for VLSI interconnects . In Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD\u201907) . IEEE, 325--330. J. V. R. Ravindra and M. B. Srinivas. 2007. A statistical model for estimating the effect of process variations on delay and slew metrics for VLSI interconnects. In Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD\u201907). IEEE, 325--330."},{"key":"e_1_2_1_29_1","volume-title":"Srinivasa Shashank Nuthakki, Debdeep Mukhopadhyay et al.","author":"Saha Sayandeep","year":"2015","unstructured":"Sayandeep Saha , Rajat Subhra Chakraborty , Srinivasa Shashank Nuthakki, Debdeep Mukhopadhyay et al. 2015 . Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability. In International Workshop on Cryptographic Hardware and Embedded Systems. Springer , 577--596. Sayandeep Saha, Rajat Subhra Chakraborty, Srinivasa Shashank Nuthakki, Debdeep Mukhopadhyay et al. 2015. Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability. In International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 577--596."},{"key":"e_1_2_1_30_1","volume-title":"Hardware IP Security and Trust","author":"Salmani Hassan","unstructured":"Hassan Salmani and Mark Tehranipoor . 2017. Digital circuit vulnerabilities to hardware Trojans . In Hardware IP Security and Trust . Springer , 37--51. Hassan Salmani and Mark Tehranipoor. 2017. Digital circuit vulnerabilities to hardware Trojans. In Hardware IP Security and Trust. Springer, 37--51."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657085"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2093547"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2520910"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.298042"},{"key":"e_1_2_1_35_1","volume-title":"Sutherland","author":"Sproull Robert F.","year":"1991","unstructured":"Robert F. Sproull and Ivan E . Sutherland . 1991 . Logical effort: Designing for speed on the back of an envelope. IEEE Advanced Research in VLSI. 1--16. Robert F. Sproull and Ivan E. Sutherland. 1991. Logical effort: Designing for speed on the back of an envelope. IEEE Advanced Research in VLSI. 1--16."},{"key":"e_1_2_1_36_1","volume-title":"Harris","author":"Sutherland Ivan Edward","year":"1999","unstructured":"Ivan Edward Sutherland , Robert F. Sproull , and David F . Harris . 1999 . Logical Effort : Designing Fast CMOS Circuits. Morgan Kaufmann . Ivan Edward Sutherland, Robert F. Sproull, and David F. Harris. 1999. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann."},{"key":"e_1_2_1_37_1","unstructured":"Synopsys. 2007. PrimeTime User Guide Version A-2007.12.  Synopsys. 2007. PrimeTime User Guide Version A-2007.12."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2016.7835569"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.61"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403703"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2014.6855579"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2013.6581574"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043570"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3229050","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3229050","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:07:35Z","timestamp":1750212455000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3229050"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7,31]]},"references-count":44,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,7,31]]}},"alternative-id":["10.1145\/3229050"],"URL":"https:\/\/doi.org\/10.1145\/3229050","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,7,31]]},"assertion":[{"value":"2017-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-04-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-10-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}