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Syst."],"published-print":{"date-parts":[[2018,9,30]]},"abstract":"<jats:p>The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.<\/jats:p>","DOI":"10.1145\/3229082","type":"journal-article","created":{"date-parts":[[2018,8,23]],"date-time":"2018-08-23T11:48:27Z","timestamp":1535024907000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Folded Circuit Synthesis"],"prefix":"10.1145","volume":"23","author":[{"given":"Inhak","family":"Han","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,8,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270347"},{"volume-title":"Proc. ACM-SIAM Symp. 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