{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T16:05:52Z","timestamp":1762272352161,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":52,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,7,15]],"date-time":"2018-07-15T00:00:00Z","timestamp":1531612800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,7,15]]},"DOI":"10.1145\/3229631.3229639","type":"proceedings-article","created":{"date-parts":[[2019,1,14]],"date-time":"2019-01-14T13:15:25Z","timestamp":1547471725000},"page":"89-96","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Architectural considerations for FPGA acceleration of machine learning applications in MapReduce"],"prefix":"10.1145","author":[{"given":"Katayoun","family":"Neshatpour","sequence":"first","affiliation":[{"name":"George Mason University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hosein Mohammadi","family":"Mokrani","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hassan","family":"Ghasemzadeh","sequence":"additional","affiliation":[{"name":"Washington State University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Setareh","family":"Rafatirad","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"George Mason University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,7,15]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"1","volume-title":"2016 49th Annual IEEE\/ACM International Symposium on. IEEE","author":"Caulfield A. M.","year":"2016","unstructured":"A. M. Caulfield and et. al, \"A cloud-scale acceleration architecture,\" in Microarchitecture (MICRO) , 2016 49th Annual IEEE\/ACM International Symposium on. IEEE , 2016 , pp. 1 -- 13 . A. M. Caulfield and et. al, \"A cloud-scale acceleration architecture,\" in Microarchitecture (MICRO), 2016 49th Annual IEEE\/ACM International Symposium on. IEEE, 2016, pp. 1--13."},{"key":"e_1_3_2_1_2_1","first-page":"13","volume-title":"2014 ACM\/IEEE 41st International Symposium on","author":"Putnam A.","year":"2014","unstructured":"A. Putnam and et al., \"A reconfigurable fabric for accelerating large-scale datacenter services,\" in Computer Architecture (ISCA) , 2014 ACM\/IEEE 41st International Symposium on , June 2014 , pp. 13 -- 24 . A. Putnam and et al., \"A reconfigurable fabric for accelerating large-scale datacenter services,\" in Computer Architecture (ISCA), 2014 ACM\/IEEE 41st International Symposium on, June 2014, pp. 13--24."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","first-page":"280","DOI":"10.1007\/978-3-642-32686-8_26","volume-title":"Smart Spaces, and Next Generation Networking","author":"Yin D.","year":"2012","unstructured":"D. Yin , G. Li et al., \"Scalable mapreduce framework on fpga accelerated commodity hardware,\" in Internet of Things , Smart Spaces, and Next Generation Networking . Springer , 2012 , pp. 280 -- 294 . D. Yin, G. Li et al., \"Scalable mapreduce framework on fpga accelerated commodity hardware,\" in Internet of Things, Smart Spaces, and Next Generation Networking. Springer, 2012, pp. 280--294."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723129"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2015.7363748"},{"key":"e_1_3_2_1_6_1","volume-title":"dissertation","author":"Ghasemi E.","year":"2015","unstructured":"E. Ghasemi , \" A scalable heterogeneous dataflow architecture for big data analytics using fpgas,\" Ph. D. dissertation , University of Toronto (Canada) , 2015 . E. Ghasemi, \"A scalable heterogeneous dataflow architecture for big data analytics using fpgas,\" Ph.D. dissertation, University of Toronto (Canada), 2015."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897972"},{"key":"e_1_3_2_1_8_1","first-page":"9","article-title":"Map-reduce processing of k-means algorithm with fpga-accelerated computer cluster","author":"Choi Y.-M.","year":"2014","unstructured":"Y.-M. Choi and H.-H. So , \" Map-reduce processing of k-means algorithm with fpga-accelerated computer cluster ,\" in IEEE ASAP , June 2014 , pp. 9 -- 16 . Y.-M. Choi and H.-H. So, \"Map-reduce processing of k-means algorithm with fpga-accelerated computer cluster,\" in IEEE ASAP, June 2014, pp. 9--16.","journal-title":"IEEE ASAP"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-016-1108-7"},{"key":"e_1_3_2_1_10_1","first-page":"679","volume-title":"Dec 2014","author":"Ho S. W.","unstructured":"S. W. Ho , M. Z. Ding , P. S. Lim , D. I. Cereno , G. Katti , T. C. Chai , and S. Bhattacharya , \" 2.5d through silicon interposer package fabrication by chip-on-wafer (cow) approach,\" in 2014 (EPTC) , Dec 2014 , pp. 679 -- 683 . S. W. Ho, M. Z. Ding, P. S. Lim, D. I. Cereno, G. Katti, T. C. Chai, and S. Bhattacharya, \"2.5d through silicon interposer package fabrication by chip-on-wafer (cow) approach,\" in 2014 (EPTC), Dec 2014, pp. 679--683."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"\"Heterogeneous 2.5d integration on through silicon interposer \" in Applied Physics Reviews 2015.  \"Heterogeneous 2.5d integration on through silicon interposer \" in Applied Physics Reviews 2015.","DOI":"10.1063\/1.4921463"},{"key":"e_1_3_2_1_12_1","first-page":"2004","article-title":"Mapreduce: simplified data processing on large clusters","author":"Dean J.","year":"2004","unstructured":"J. Dean and S. Ghemawat , \" Mapreduce: simplified data processing on large clusters ,\" in OSDI 2004 , 2004 . J. Dean and S. Ghemawat, \"Mapreduce: simplified data processing on large clusters,\" in OSDI 2004, 2004.","journal-title":"OSDI"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.77"},{"key":"e_1_3_2_1_14_1","unstructured":"\"Hadoop programming with arbitrary languages \" https:\/\/rcc.fsu.edu\/docs\/hadoop-programming-arbitrary-languages.  \"Hadoop programming with arbitrary languages \" https:\/\/rcc.fsu.edu\/docs\/hadoop-programming-arbitrary-languages."},{"key":"e_1_3_2_1_15_1","unstructured":"\"Intel vtune amplifier xe performance profiler.\" http:\/\/software.intel.com\/en-us\/articles\/intel-vtune-amplifier-xe\/ accessed: 2014-11-30.  \"Intel vtune amplifier xe performance profiler.\" http:\/\/software.intel.com\/en-us\/articles\/intel-vtune-amplifier-xe\/ accessed: 2014-11-30."},{"key":"e_1_3_2_1_16_1","unstructured":"\"Vivado design suite user guide: High-level synthesis \" http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2013_2\/ug902-vivado-high-level-synthesis.pdf.  \"Vivado design suite user guide: High-level synthesis \" http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2013_2\/ug902-vivado-high-level-synthesis.pdf."},{"key":"e_1_3_2_1_17_1","volume-title":"Hadoop: The Definitive Guide","author":"White T.","year":"2009","unstructured":"T. White , Hadoop: The Definitive Guide . O'Reilly Media, Inc. , 2009 . T. White, Hadoop: The Definitive Guide. O'Reilly Media, Inc., 2009."},{"key":"e_1_3_2_1_18_1","volume-title":"A survey on hardware\/software codesign representation models","author":"Cortes L. A.","year":"1999","unstructured":"L. A. Cortes , L. Alej , R. Corts , P. Eles , and Z. Peng , \" A survey on hardware\/software codesign representation models ,\" 1999 . L. A. Cortes, L. Alej, R. Corts, P. Eles, and Z. Peng, \"A survey on hardware\/software codesign representation models,\" 1999."},{"key":"e_1_3_2_1_19_1","unstructured":"P. Eles and et. al \"Scheduling of conditional process graphs for the synthesis of embedded systems \" in DATE 1998.   P. Eles and et. al \"Scheduling of conditional process graphs for the synthesis of embedded systems \" in DATE 1998."},{"key":"e_1_3_2_1_20_1","unstructured":"\"Logicore axi dma \" Product Guide for Vivado Design Suite 2013.  \"Logicore axi dma \" Product Guide for Vivado Design Suite 2013."},{"key":"e_1_3_2_1_21_1","unstructured":"\"white paper understanding performance of pci express sytems \" https:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp350.pdf.  \"white paper understanding performance of pci express sytems \" https:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp350.pdf."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-10665-1_71"},{"key":"e_1_3_2_1_23_1","first-page":"513","volume-title":"Modelling and Simulation","author":"Anchalia P. P.","year":"2014","unstructured":"P. P. Anchalia and K. Roy , \" The k-nearest neighbor algorithm using mapreduce paradigm,\" in Proceedings of the Fifth International Conference on Intelligent Systems , Modelling and Simulation , 2014 , pp. 513 -- 518 . P. P. Anchalia and K. Roy, \"The k-nearest neighbor algorithm using mapreduce paradigm,\" in Proceedings of the Fifth International Conference on Intelligent Systems, Modelling and Simulation, 2014, pp. 513--518."},{"key":"e_1_3_2_1_24_1","unstructured":"B. Bayramli \"Svd factorization for tall-and-fat matrices on map\/reduce architectures \" arXiv:1310.4664 2014.  B. Bayramli \"Svd factorization for tall-and-fat matrices on map\/reduce architectures \" arXiv:1310.4664 2014."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.18626"},{"key":"e_1_3_2_1_26_1","unstructured":"A. J. Mount \"Large data logistic regression (with example hadoop code) \" http:\/\/www.win-vector.com\/blog\/2010\/12\/large-data-logistic-regression-with-example-hadoop-code\/ accessed: 2015-5-12.  A. J. Mount \"Large data logistic regression (with example hadoop code) \" http:\/\/www.win-vector.com\/blog\/2010\/12\/large-data-logistic-regression-with-example-hadoop-code\/ accessed: 2015-5-12."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSS.2014.15"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/502512.502527"},{"key":"e_1_3_2_1_29_1","first-page":"6","article-title":"Naive bayes","volume":"31","author":"N. H.","year":"2011","unstructured":"N. H. N. , \" Naive bayes ,\" IEEE Micro , vol. 31 , pp. 6 -- 15 , 2011 . N. H. N., \"Naive bayes,\" IEEE Micro, vol. 31, pp. 6--15, 2011.","journal-title":"IEEE Micro"},{"key":"e_1_3_2_1_30_1","unstructured":"\"Wattsuppro power meter \" http:\/\/www.wattsupmeters.com\/secure\/index accessed: 2014-11-30.  \"Wattsuppro power meter \" http:\/\/www.wattsupmeters.com\/secure\/index accessed: 2014-11-30."},{"key":"e_1_3_2_1_31_1","unstructured":"\"Industry's lowest power pci express 3.1 ip solution for mobile socs \" http:\/\/www.synopsys.com\/designware.  \"Industry's lowest power pci express 3.1 ip solution for mobile socs \" http:\/\/www.synopsys.com\/designware."},{"key":"e_1_3_2_1_32_1","first-page":"118","volume-title":"Conf. Big Data","author":"Honjo T.","year":"2013","unstructured":"T. Honjo and K. Oikawa , \" Hardware acceleration of hadoop mapreduce,\" in IEEE Int . Conf. Big Data , Oct 2013 , pp. 118 -- 124 . T. Honjo and K. Oikawa, \"Hardware acceleration of hadoop mapreduce,\" in IEEE Int. Conf. Big Data, Oct 2013, pp. 118--124."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.14778\/1920841.1920903"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/GCC.2009.19"},{"key":"e_1_3_2_1_35_1","first-page":"29","volume-title":"USA","author":"Zaharia M.","year":"2008","unstructured":"M. Zaharia , A. Konwinski , A. D. Joseph , R. Katz , and I. Stoica , \" Improving mapreduce performance in heterogeneous environments,\" in OSDI, Berkeley, CA , USA , 2008 , pp. 29 -- 42 . M. Zaharia, A. Konwinski, A. D. Joseph, R. Katz, and I. Stoica, \"Improving mapreduce performance in heterogeneous environments,\" in OSDI, Berkeley, CA, USA, 2008, pp. 29--42."},{"key":"e_1_3_2_1_36_1","first-page":"153","article-title":"Characterizing hadoop applications on microservers for performance and energy efficiency optimizations","author":"Malik M.","year":"2016","unstructured":"M. Malik , A. Sasan , R. Joshi , S. Rafatirah , and H. Homayoun , \" Characterizing hadoop applications on microservers for performance and energy efficiency optimizations ,\" in ISPASS. IEEE , 2016 , pp. 153 -- 154 . M. Malik, A. Sasan, R. Joshi, S. Rafatirah, and H. Homayoun, \"Characterizing hadoop applications on microservers for performance and energy efficiency optimizations,\" in ISPASS. IEEE, 2016, pp. 153--154.","journal-title":"ISPASS. IEEE"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.102"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"e_1_3_2_1_39_1","first-page":"1","volume-title":"2010 International Conference on","author":"Stolz L.","year":"2010","unstructured":"L. Stolz , H. Endt , M. Vaaraniemi , D. Zehe , and W. Stechele , \" Energy consumption of graphic processing units with respect to automotive use-cases,\" in Energy Aware Computing (ICEAC) , 2010 International Conference on , Dec 2010 , pp. 1 -- 4 . L. Stolz, H. Endt, M. Vaaraniemi, D. Zehe, and W. Stechele, \"Energy consumption of graphic processing units with respect to automotive use-cases,\" in Energy Aware Computing (ICEAC), 2010 International Conference on, Dec 2010, pp. 1--4."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145704"},{"key":"e_1_3_2_1_41_1","first-page":"450","volume-title":"Dec 2013","author":"Lin Z.","unstructured":"Z. Lin and P. Chow , \" Zcluster: A zynq-based hadoop cluster,\" in 2013 FTP , Dec 2013 , pp. 450 -- 453 . Z. Lin and P. Chow, \"Zcluster: A zynq-based hadoop cluster,\" in 2013 FTP, Dec 2013, pp. 450--453."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554700"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCGrid.2015.165"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.59"},{"key":"e_1_3_2_1_45_1","first-page":"1134","volume-title":"2016 IEEE International Symposium on. IEEE","author":"Neshatpour K.","year":"2016","unstructured":"K. Neshatpour , A. Koohi , F. Farahmand , R. Joshi , S. Rafatirad , A. Sasan , and H. Homayoun , \" Big biomedical image processing hardware acceleration: A case study for k-means and image filtering,\" in Circuits and Systems (ISCAS) , 2016 IEEE International Symposium on. IEEE , 2016 , pp. 1134 -- 1137 . K. Neshatpour, A. Koohi, F. Farahmand, R. Joshi, S. Rafatirad, A. Sasan, and H. Homayoun, \"Big biomedical image processing hardware acceleration: A case study for k-means and image filtering,\" in Circuits and Systems (ISCAS), 2016 IEEE International Symposium on. IEEE, 2016, pp. 1134--1137."},{"key":"e_1_3_2_1_46_1","volume-title":"Big data analytics on heterogeneous accelerator architectures,\" in CODES+ISSS","author":"Neshatpour K.","year":"2016","unstructured":"K. Neshatpour , A. Sasan , and H. Homayoun , \" Big data analytics on heterogeneous accelerator architectures,\" in CODES+ISSS , 2016 , p. 16. K. Neshatpour, A. Sasan, and H. Homayoun, \"Big data analytics on heterogeneous accelerator architectures,\" in CODES+ISSS, 2016, p. 16."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2018.02.004"},{"key":"e_1_3_2_1_48_1","first-page":"1480","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"Malik M.","year":"2017","unstructured":"M. Malik , K. Neshatpour , T. Mohsenin , A. Sasan , and H. Homayoun , \" Big vs little core for energy-efficient hadoop computing,\" in 2017 Design , Automation & Test in Europe Conference & Exhibition (DATE). IEEE , 2017 , pp. 1480 -- 1485 . M. Malik, K. Neshatpour, T. Mohsenin, A. Sasan, and H. Homayoun, \"Big vs little core for energy-efficient hadoop computing,\" in 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017, pp. 1480--1485."},{"key":"e_1_3_2_1_49_1","article-title":"Hadoop workloads characterization for performance and energy efficiency optimizations on microservers","author":"Malik M.","year":"2017","unstructured":"M. Malik , K. Neshatpour , S. Rafatirad , and H. Homayoun , \" Hadoop workloads characterization for performance and energy efficiency optimizations on microservers ,\" IEEE Transactions on Multi-Scale Computing Systems , 2017 . M. Malik, K. Neshatpour, S. Rafatirad, and H. Homayoun, \"Hadoop workloads characterization for performance and energy efficiency optimizations on microservers,\" IEEE Transactions on Multi-Scale Computing Systems, 2017.","journal-title":"IEEE Transactions on Multi-Scale Computing Systems"},{"key":"e_1_3_2_1_50_1","volume-title":"Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning,\" in ASP-DAC","author":"Sayadi H.","year":"2018","unstructured":"H. Sayadi , D. Pathak , I. Savidis , and H. Homayoun , \" Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning,\" in ASP-DAC , 2018 . H. Sayadi, D. Pathak, I. Savidis, and H. Homayoun, \"Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning,\" in ASP-DAC, 2018."},{"key":"e_1_3_2_1_51_1","volume-title":"Machine learning-based approaches for energy-efficiency prediction and scheduling in composite cores architectures,\" in ICCD","author":"Sayadi H.","year":"2017","unstructured":"H. Sayadi , N. Patel , A. Sasan , and H. Homayoun , \" Machine learning-based approaches for energy-efficiency prediction and scheduling in composite cores architectures,\" in ICCD , 2017 . H. Sayadi, N. Patel, A. Sasan, and H. Homayoun, \"Machine learning-based approaches for energy-efficiency prediction and scheduling in composite cores architectures,\" in ICCD, 2017."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"crossref","unstructured":"K. Neshatpour H. Mohammadi Makrani A. Sasan and H. H. Hassan Ghasemzadeh Setareh Rafatirad \"Design space exploration for acceleration of machine learning applications \" FCCM 2018.  K. Neshatpour H. Mohammadi Makrani A. Sasan and H. H. Hassan Ghasemzadeh Setareh Rafatirad \"Design space exploration for acceleration of machine learning applications \" FCCM 2018.","DOI":"10.1109\/FCCM.2018.00055"}],"event":{"name":"SAMOS XVIII: Architectures, Modeling, and Simulation","acronym":"SAMOS XVIII","location":"Pythagorion Greece"},"container-title":["Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3229631.3229639","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3229631.3229639","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:07:38Z","timestamp":1750212458000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3229631.3229639"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7,15]]},"references-count":52,"alternative-id":["10.1145\/3229631.3229639","10.1145\/3229631"],"URL":"https:\/\/doi.org\/10.1145\/3229631.3229639","relation":{},"subject":[],"published":{"date-parts":[[2018,7,15]]},"assertion":[{"value":"2018-07-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}