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Syst."],"published-print":{"date-parts":[[2019,7,31]]},"abstract":"<jats:p>XDense is a novel wired 2D mesh grid sensor network system for application scenarios that benefit from densely deployed sensing (e.g., thousands of sensors per square meter). It was conceived for cyber-physical systems that require real-time sensing and actuation, like active flow control on aircraft wing surfaces. XDense communication and distributed processing capabilities are designed to enable complex feature extraction within bounded time and in a responsive manner. In this article, we tackle the issue of deterministic behavior of XDense. We present a methodology that uses traffic-shaping heuristics to guarantee bounded communication delays and the fulfillment of memory requirements. We evaluate the model for varied network configurations and workload, and present a comparative performance analysis in terms of link utilization, queue size, and execution time. With the proposed traffic-shaping heuristics, we endow XDense with the capabilities required for real-time applications.<\/jats:p>","DOI":"10.1145\/3230872","type":"journal-article","created":{"date-parts":[[2019,8,20]],"date-time":"2019-08-20T19:51:56Z","timestamp":1566330716000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Extensive Analysis of a Real-Time Dense Wired Sensor Network Based on Traffic Shaping"],"prefix":"10.1145","volume":"3","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3163-9136","authenticated-orcid":false,"given":"Jo\u00e3o","family":"Loureiro","sequence":"first","affiliation":[{"name":"CISTER\/INESC-TEC, ISEP, Polytechnic Institute of Porto"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Raghuraman","family":"Rangarajan","sequence":"additional","affiliation":[{"name":"CISTER\/INESC-TEC, ISEP, Polytechnic Institute of Porto"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Borislav","family":"Nikolic","sequence":"additional","affiliation":[{"name":"CISTER\/INESC-TEC, ISEP, Polytechnic Institute of Porto; Institute of Computer and Network Engineering, Technische Universit\u00e4t Braunschweig, Braunschweig, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Leandro Soares","family":"Indrusiak","sequence":"additional","affiliation":[{"name":"University of York, Heslington, York, United Kingdom"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eduardo","family":"Tovar","sequence":"additional","affiliation":[{"name":"CISTER\/INESC-TEC, ISEP, Polytechnic Institute of Porto"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2019,8,20]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"21","article-title":"Survey of network on chip (NoC) architectures 8 contributions","volume":"3","author":"Agarwal Ankur","year":"2009","unstructured":"Ankur Agarwal , Cyril Iskander , and Ravi Shankar . 2009 . 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