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Andrieu , \" Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation,\" IEDM , pp. 20.3.1 -- 20.3.4 , 2017 . F. Andrieu et al., \"Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation,\" IEDM, pp. 20.3.1--20.3.4, 2017."},{"key":"e_1_3_2_1_9_1","first-page":"328","volume-title":"Digest of Technical Papers","author":"Verma N.","year":"2007","unstructured":"N. Verma , \" A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy,\" ISSCC , Digest of Technical Papers , pp. 328 -- 606 , 2007 . N. Verma et al., \"A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy,\" ISSCC, Digest of Technical Papers, pp. 328--606, 2007."},{"key":"e_1_3_2_1_10_1","first-page":"T48","volume-title":"Symposium on VLSI Technology","author":"Batude P.","year":"2015","unstructured":"P. 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