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Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). An STT-based LUT with a significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance, and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT-based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study, conducted on a large number of standard circuit benchmarks, concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact on the performance of the circuit. We also tested these techniques against satisfiability attacks developed recently and show that these techniques also render more advanced reverse-engineering techniques computationally infeasible.<\/jats:p>","DOI":"10.1145\/3236622","type":"journal-article","created":{"date-parts":[[2018,12,21]],"date-time":"2018-12-21T13:39:21Z","timestamp":1545399561000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering"],"prefix":"10.1145","volume":"23","author":[{"given":"Ted","family":"Winograd","sequence":"first","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gaurav","family":"Shenoy","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hassan","family":"Salmani","sequence":"additional","affiliation":[{"name":"Howard University, Washington, DC, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Mahmoodi","sequence":"additional","affiliation":[{"name":"San Francisco State University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Setareh","family":"Rafatirad","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"George Mason University, Fairfax, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,12,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2905020"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2016.7905481"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2016.7905481"},{"volume-title":"Security engineering: A guide to building dependable distributed systems, physical tamper resistance","author":"Anderson R.","key":"e_1_2_1_5_1","unstructured":"R. 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