{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,21]],"date-time":"2026-03-21T19:15:18Z","timestamp":1774120518800,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1145\/3240302.3240306","type":"proceedings-article","created":{"date-parts":[[2019,1,4]],"date-time":"2019-01-04T13:33:56Z","timestamp":1546608836000},"page":"55-66","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A load balancing technique for memory channels"],"prefix":"10.1145","author":[{"given":"Byoungchan","family":"Oh","sequence":"first","affiliation":[{"name":"University of Michigan"}]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}]},{"given":"Jeongseob","family":"Ahn","sequence":"additional","affiliation":[{"name":"Ajou University, Suwon, Korea"}]},{"given":"Bingchao","family":"Li","sequence":"additional","affiliation":[{"name":"Civil Aviation University of China, Tianjin, China"}]},{"given":"Ronald G.","family":"Dreslinski","sequence":"additional","affiliation":[{"name":"University of Michigan"}]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[{"name":"University of Michigan"}]}],"member":"320","published-online":{"date-parts":[[2018,10]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"AMD. 2015. Inside pascal: NVIDIA's newest computing platform. https:\/\/www.amd.com\/en\/technologies\/hbm. (2015).  AMD. 2015. Inside pascal: NVIDIA's newest computing platform. https:\/\/www.amd.com\/en\/technologies\/hbm. (2015)."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337207"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/324133.324234"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402918"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1002\/widm.1232"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.16"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.58"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424433"},{"key":"e_1_3_2_1_11_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE)","author":"Chen Ke","year":"2012","unstructured":"Ke Chen , Sheng Li , Naveen Muralimanohar , Jung Ho Ahn , Jay B Brockman , and Norman P Jouppi . 2012 . CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. In Design , Automation & Test in Europe Conference & Exhibition (DATE) , 2012. IEEE, 33--38. Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B Brockman, and Norman P Jouppi. 2012. CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012. IEEE, 33--38."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1002\/widm.1194"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3245733"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.760380"},{"key":"e_1_3_2_1_16_1","unstructured":"Intel. 2012. DRAM Controllers for System Designers. https:\/\/www.altera.com\/solutions\/technology\/system-design\/articles\/_2012\/dram-controller-system-designer.html. (2012).  Intel. 2012. DRAM Controllers for System Designers. https:\/\/www.altera.com\/solutions\/technology\/system-design\/articles\/_2012\/dram-controller-system-designer.html. (2012)."},{"key":"e_1_3_2_1_17_1","unstructured":"JEDEC. 2013. High Bandwidth Memory (HBM) DRAM. https:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD235A.pdf. (2013).  JEDEC. 2013. High Bandwidth Memory (HBM) DRAM. https:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD235A.pdf. (2013)."},{"key":"e_1_3_2_1_18_1","unstructured":"JEDEC. 2016. GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD. https:\/\/www.jedec.org\/system\/files\/docs\/JESD212C.pdf. (2016).  JEDEC. 2016. GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD. https:\/\/www.jedec.org\/system\/files\/docs\/JESD212C.pdf. (2016)."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"e_1_3_2_1_20_1","volume-title":"High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on. IEEE, 1--12","author":"Kim Yoongu","year":"2010","unstructured":"Yoongu Kim , Dongsu Han , Onur Mutlu , and Mor Harchol-Balter . 2010 . ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers . In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on. IEEE, 1--12 . Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter. 2010. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on. IEEE, 1--12."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1296907.1296909"},{"key":"e_1_3_2_1_22_1","volume-title":"Building intuition","author":"Little John DC","unstructured":"John DC Little and Stephen C Graves . 2008. Little's law . In Building intuition . Springer , 81--100. John DC Little and Stephen C Graves. 2008. Little's law. In Building intuition. Springer, 81--100."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1870952"},{"key":"e_1_3_2_1_24_1","unstructured":"MICRON. 2014. DDR4 SDRAM. https:\/\/www.micron.com\/~\/media\/documents\/products\/data-sheet\/dram\/ddr4\/4gb_ddr4_dram_2e0d.pdf. (2014).  MICRON. 2014. DDR4 SDRAM. https:\/\/www.micron.com\/~\/media\/documents\/products\/data-sheet\/dram\/ddr4\/4gb_ddr4_dram_2e0d.pdf. (2014)."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.963420"},{"key":"e_1_3_2_1_26_1","unstructured":"NVIDA. 2016. Inside pascal: NVIDIA's newest computing platform. https:\/\/devblogs.nvidia.com\/inside-pascal. (2016).  NVIDA. 2016. Inside pascal: NVIDIA's newest computing platform. https:\/\/devblogs.nvidia.com\/inside-pascal. (2016)."},{"key":"e_1_3_2_1_27_1","volume-title":"Computer graphics forum","author":"Owens John D","unstructured":"John D Owens , David Luebke , Naga Govindaraju , Mark Harris , Jens Kr\u00fcger , Aaron E Lefohn , and Timothy J Purcell . 2007. A survey of general-purpose computation on graphics hardware . In Computer graphics forum , Vol. 26 . Wiley Online Library , 80--113. John D Owens, David Luebke, Naga Govindaraju, Mark Harris, Jens Kr\u00fcger, Aaron E Lefohn, and Timothy J Purcell. 2007. A survey of general-purpose computation on graphics hardware. In Computer graphics forum, Vol. 26. Wiley Online Library, 80--113."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264201"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"e_1_3_2_1_30_1","first-page":"127","article-title":"Method and apparatus for out of order memory scheduling. (Oct. 24 2006)","volume":"7","author":"Rotithor Hemant G","year":"2006","unstructured":"Hemant G Rotithor , Randy B Osborne , and Nagi Aboulenein . 2006 . Method and apparatus for out of order memory scheduling. (Oct. 24 2006) . US Patent 7 , 127 ,574. Hemant G Rotithor, Randy B Osborne, and Nagi Aboulenein. 2006. Method and apparatus for out of order memory scheduling. (Oct. 24 2006). US Patent 7,127,574.","journal-title":"US Patent"},{"key":"e_1_3_2_1_31_1","unstructured":"Samsung Semiconductor. 2016. Research collaboration communications. (2016).  Samsung Semiconductor. 2016. Research collaboration communications. (2016)."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1186\/s40537-014-0008-6"},{"key":"e_1_3_2_1_33_1","volume-title":"Geng Daniel Liu, and Wen-mei W Hwu","author":"Stratton John A","year":"2012","unstructured":"John A Stratton , Christopher Rodrigues , I- Jui Sung , Nady Obeid , Li-Wen Chang , Nasser Anssari , Geng Daniel Liu, and Wen-mei W Hwu . 2012 . Parboil : A revised benchmark suite for scientific and commercial throughput computing. Center for Reliable and High-Performance Computing 127 (2012). John A Stratton, Christopher Rodrigues, I-Jui Sung, Nady Obeid, Li-Wen Chang, Nasser Anssari, Geng Daniel Liu, and Wen-mei W Hwu. 2012. Parboil: A revised benchmark suite for scientific and commercial throughput computing. Center for Reliable and High-Performance Computing 127 (2012)."},{"key":"e_1_3_2_1_34_1","unstructured":"Oklahoma State University. 2017. FreePDK: Unleashing VLSI to the Masses. https:\/\/vlsiarch.ecen.okstate.edu\/flows\/. (2017).  Oklahoma State University. 2017. FreePDK: Unleashing VLSI to the Masses. https:\/\/vlsiarch.ecen.okstate.edu\/flows\/. (2017)."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2479595"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.122"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669119"},{"key":"e_1_3_2_1_38_1","first-page":"630","article-title":"Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order. (May 13 1997)","volume":"5","author":"Zuravleff William K","year":"1997","unstructured":"William K Zuravleff and Timothy Robinson . 1997 . Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order. (May 13 1997) . US Patent 5 , 630 ,096. William K Zuravleff and Timothy Robinson. 1997. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order. (May 13 1997). US Patent 5,630,096.","journal-title":"US Patent"}],"event":{"name":"MEMSYS '18: The International Symposium on Memory Systems","location":"Alexandria Virginia USA","acronym":"MEMSYS '18"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240302.3240306","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3240302.3240306","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:01Z","timestamp":1750208881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240302.3240306"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":38,"alternative-id":["10.1145\/3240302.3240306","10.1145\/3240302"],"URL":"https:\/\/doi.org\/10.1145\/3240302.3240306","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]},"assertion":[{"value":"2018-10-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}