{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:32:17Z","timestamp":1750221137040,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":89,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100003816","name":"Huawei Technologies","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003816","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Eurolab-4-HPC","award":["H2020 project 671610"],"award-info":[{"award-number":["H2020 project 671610"]}]},{"name":"Nano-Tera.ch"},{"name":"Swiss National Science Foundation","award":["200021_165749"],"award-info":[{"award-number":["200021_165749"]}]},{"name":"SNF","award":["20CH21_155014"],"award-info":[{"award-number":["20CH21_155014"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1145\/3240302.3240310","type":"proceedings-article","created":{"date-parts":[[2019,1,4]],"date-time":"2019-01-04T13:33:56Z","timestamp":1546608836000},"page":"3-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Design guidelines for high-performance SCM hierarchies"],"prefix":"10.1145","author":[{"given":"Dmitrii","family":"Ustiugov","sequence":"first","affiliation":[{"name":"EcoCloud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexandros","family":"Daglis","sequence":"additional","affiliation":[{"name":"EcoCloud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Picorel","sequence":"additional","affiliation":[{"name":"Huawei Technologies"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Sutherland","sequence":"additional","affiliation":[{"name":"EcoCloud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edouard","family":"Bugnion","sequence":"additional","affiliation":[{"name":"EcoCloud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Babak","family":"Falsafi","sequence":"additional","affiliation":[{"name":"EcoCloud"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dionisios","family":"Pnevmatikatos","sequence":"additional","affiliation":[{"name":"FORTH-ICS &amp; ECE-TUC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,10]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037706"},{"key":"e_1_3_2_1_2_1","unstructured":"Amazon. 2016. EC2 in-memory processing update: Instances with 4 to 16 TB of memory + scale-out SAP HANA to 34 TB. Available at aws.amazon.com\/blogs\/aws\/ec2-in-memory-processing-update-instances-with-4-to-16-tb-of-memory-scale-out-sap-hana-to-34-tb.  Amazon. 2016. EC2 in-memory processing update: Instances with 4 to 16 TB of memory + scale-out SAP HANA to 34 TB. Available at aws.amazon.com\/blogs\/aws\/ec2-in-memory-processing-update-instances-with-4-to-16-tb-of-memory-scale-out-sap-hana-to-34-tb."},{"key":"e_1_3_2_1_3_1","unstructured":"AMD. 2016. High Bandwidth Memory reinventing memory technology. Available at www.amd.com\/en-us\/innovations\/software-technologies\/hbm.  AMD. 2016. High Bandwidth Memory reinventing memory technology. Available at www.amd.com\/en-us\/innovations\/software-technologies\/hbm."},{"key":"e_1_3_2_1_4_1","unstructured":"AnandTech. 2017. NVIDIA bumps all Tesla V100 models to 32GB effective immediately. Available at www.anandtech.com\/show\/12576\/nvidia-bumps-all-tesla-v100-models-to-32gb.  AnandTech. 2017. NVIDIA bumps all Tesla V100 models to 32GB effective immediately. Available at www.anandtech.com\/show\/12576\/nvidia-bumps-all-tesla-v100-models-to-32gb."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.66"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463676.2465296"},{"key":"e_1_3_2_1_7_1","unstructured":"Arstechnica. 2016. HBM3: Cheaper up to 64GB on-package and terabytes-per-second bandwidth. Available at arstechnica.com\/gadgets\/2016\/08\/hbm3-details-price-bandwidth.  Arstechnica. 2016. HBM3: Cheaper up to 64GB on-package and terabytes-per-second bandwidth. Available at arstechnica.com\/gadgets\/2016\/08\/hbm3-details-price-bandwidth."},{"key":"e_1_3_2_1_8_1","unstructured":"Aravinthan Athmanathan. 2016. Multi-level cell phase-change memory - modeling and reliability framework. Ph.D. Dissertation. EPFL.  Aravinthan Athmanathan. 2016. Multi-level cell phase-change memory - modeling and reliability framework. Ph.D. Dissertation. EPFL."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00061"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3064176.3064193"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1298306.1298309"},{"volume-title":"Proceedings of the 5th Biennial Conference on Innovative Data Systems Research (CIDR).","year":"2011","author":"Chen Shimin","key":"e_1_3_2_1_12_1"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.63"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750387"},{"volume-title":"Proceedings of the 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO).","author":"Jaleel Aamer","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132402.3132404"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2062811"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2815400.2815425"},{"key":"e_1_3_2_1_19_1","unstructured":"DRAMeXchange. 2018. Available at www.dramexchange.com.  DRAMeXchange. 2018. Available at www.dramexchange.com."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2901318.2901344"},{"key":"e_1_3_2_1_21_1","unstructured":"ExtremeTech. 2017. Intel's new Stratix 10 MX FPGA taps HBM2 for massive memory bandwidth. Available at www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/wp\/wp-01264-stratix10mx-devices-solve-memory-bandwidth-challenge.pdf.  ExtremeTech. 2017. Intel's new Stratix 10 MX FPGA taps HBM2 for massive memory bandwidth. Available at www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/wp\/wp-01264-stratix10mx-devices-solve-memory-bandwidth-challenge.pdf."},{"key":"e_1_3_2_1_22_1","unstructured":"ExtremeTech. 2017. Qualcomm announces 48-core Falkor CPUs to run Microsoft Windows Server. Available at www.extremetech.com\/computing\/245496-qualcomm-announces-partnership-microsoft-48-core-falkor-cpus-run-windows-server.  ExtremeTech. 2017. Qualcomm announces 48-core Falkor CPUs to run Microsoft Windows Server. Available at www.extremetech.com\/computing\/245496-qualcomm-announces-partnership-microsoft-48-core-falkor-cpus-run-windows-server."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2038916.2038939"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2543697"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"volume-title":"Proceedings of the 12th Symposium on Operating System Design and Implementation (OSDI).","year":"2016","author":"Gao Peter Xiang","key":"e_1_3_2_1_26_1"},{"key":"e_1_3_2_1_27_1","unstructured":"Linley Group. 2017. Epyc relaunches AMD into servers. Microprocessor Report (June 2017).  Linley Group. 2017. Epyc relaunches AMD into servers. Microprocessor Report (June 2017)."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155642"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2987550.2987570"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"e_1_3_2_1_31_1","unstructured":"Intel. 2016. Intel Optane memory. Available at www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/optane-memory.html.  Intel. 2016. Intel Optane memory. Available at www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/optane-memory.html."},{"key":"e_1_3_2_1_32_1","unstructured":"JEDEC. 2013. Wide I\/O 2 standard. Available at www.jedec.org\/standards-documents\/results\/jesd229-2.  JEDEC. 2013. Wide I\/O 2 standard. Available at www.jedec.org\/standards-documents\/results\/jesd229-2."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.51"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.10"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416642"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_3_2_1_38_1","unstructured":"Gosia Jurczak. 2015. Advances and trends of RRAM technology. Available at www.semicontaiwan.org\/en\/sites\/semicontaiwan.org\/files\/data15\/docs\/2_5._advances_and_trends_in_rram_technology_semicon_taiwan_2015_final.pdf.  Gosia Jurczak. 2015. Advances and trends of RRAM technology. Available at www.semicontaiwan.org\/en\/sites\/semicontaiwan.org\/files\/data15\/docs\/2_5._advances_and_trends_in_rram_technology_semicon_taiwan_2015_final.pdf."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080236"},{"volume-title":"Memory-Driven Computing. In Proceedings of 15th USENIX Conference on File and Storage Technologies (FAST).","year":"2017","author":"Keeton Kimberly","key":"e_1_3_2_1_41_1"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750383"},{"key":"e_1_3_2_1_44_1","unstructured":"Linley Group. 2015. 3D XPoint fetches data in a flash. Microprocessor Report (September 2015).  Linley Group. 2015. 3D XPoint fetches data in a flash. Microprocessor Report (September 2015)."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037714"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337217"},{"key":"e_1_3_2_1_48_1","unstructured":"Darsen Lu. 2016. Tutorial on emerging memory devices. Available at people.oregonstate.edu\/~sllu\/Micro_MT\/presentations\/micro16_emerging_mem_tutorial_darsen.pdf.  Darsen Lu. 2016. Tutorial on emerging memory devices. Available at people.oregonstate.edu\/~sllu\/Micro_MT\/presentations\/micro16_emerging_mem_tutorial_darsen.pdf."},{"key":"e_1_3_2_1_49_1","unstructured":"Micron Technology Inc. 2014. Hybrid Memory Cube second generation. Available at investors.micron.com\/releasedetail.cfm?ReleaseID=828028.  Micron Technology Inc. 2014. Hybrid Memory Cube second generation. Available at investors.micron.com\/releasedetail.cfm?ReleaseID=828028."},{"key":"e_1_3_2_1_50_1","unstructured":"Micron Technology Inc. 2018. DDR4 SDRAM datasheets. Available at www.micron.com\/products\/dram\/ddr4-sdram.  Micron Technology Inc. 2018. DDR4 SDRAM datasheets. Available at www.micron.com\/products\/dram\/ddr4-sdram."},{"key":"e_1_3_2_1_51_1","unstructured":"Microsoft. 2016. Open CloudServer OCS V2.1 specification. Available at www.opencompute.org\/wiki\/Server\/SpecsAndDesigns.  Microsoft. 2016. Open CloudServer OCS V2.1 specification. Available at www.opencompute.org\/wiki\/Server\/SpecsAndDesigns."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037730"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/2987550.2987577"},{"key":"e_1_3_2_1_54_1","unstructured":"Open Compute Project. 2017. Open Rack Standard v2.0. Available at www.opencompute.org\/wiki\/Open_Rack\/SpecsAndDesigns.  Open Compute Project. 2017. Open Rack Standard v2.0. Available at www.opencompute.org\/wiki\/Open_Rack\/SpecsAndDesigns."},{"key":"e_1_3_2_1_55_1","unstructured":"PCGamer. 2017. What to expect from the next generation of graphics card memory. Available at www.pcgamer.com\/what-to-expect-from-the-next-generation-of-graphics-card-memory.  PCGamer. 2017. What to expect from the next generation of graphics card memory. Available at www.pcgamer.com\/what-to-expect-from-the-next-generation-of-graphics-card-memory."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815981"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"volume-title":"Proceedings of the 1st Symposium on Networked Systems Design and Implementation (NSDI).","year":"2004","author":"Ramasubramanian Venugopalan","key":"e_1_3_2_1_60_1"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540712"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950389"},{"key":"e_1_3_2_1_64_1","unstructured":"Siva Sivaram. 2016. Storage Class Memory: Learning from 3D NAND. Available at www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160809_Keynote4_WD_Sivaram.pdf.  Siva Sivaram. 2016. Storage Class Memory: Learning from 3D NAND. Available at www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2016\/20160809_Keynote4_WD_Sivaram.pdf."},{"key":"e_1_3_2_1_65_1","unstructured":"SNIA. 2016. NVDIMM - changes are here so what's next. Available at www.snia.org\/sites\/default\/files\/SSSI\/NVDIMM%20-%20Changes%20are%20Here%20So%20What's%20Next%20-%20final.pdf.  SNIA. 2016. NVDIMM - changes are here so what's next. Available at www.snia.org\/sites\/default\/files\/SSSI\/NVDIMM%20-%20Changes%20are%20Here%20So%20What's%20Next%20-%20final.pdf."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495263"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815972"},{"key":"e_1_3_2_1_70_1","unstructured":"Tom's Hardware. 2017. Hot Chips 2017: A closer look at Google's TPU v2. Available at www.tomshardware.com\/news\/tpu-v2-google-machine-learning 35370.html.  Tom's Hardware. 2017. Hot Chips 2017: A closer look at Google's TPU v2. Available at www.tomshardware.com\/news\/tpu-v2-google-machine-learning 35370.html."},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732269.2732277"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.32"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.44"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/2667105"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.79"},{"key":"e_1_3_2_1_76_1","unstructured":"Mike Wissolik Darren Zacher Anthony Torza and Brandon Da. 2017. Virtex UltraScale+ HBM FPGA: A revolutionary increase in memory performance. Xilinx Whitepaper (2017).  Mike Wissolik Darren Zacher Anthony Torza and Brandon Da. 2017. Virtex UltraScale+ HBM FPGA: A revolutionary increase in memory performance. Xilinx Whitepaper (2017)."},{"key":"e_1_3_2_1_77_1","unstructured":"HSP Wong C Ahn J Cao HY Chen SW Fong Z Jiang C Neumann S Qin J Sohn Y Wu etal 2016. Stanford memory trends. Technical Report. Stanford University.  HSP Wong C Ahn J Cao HY Chen SW Fong Z Jiang C Neumann S Qin J Sohn Y Wu et al. 2016. Stanford memory trends. Technical Report. Stanford University."},{"key":"e_1_3_2_1_78_1","unstructured":"Computer World. 2016. FAQ: 3D XPoint memory NAND flash killer or DRAM replacement? Available at www.computerworld.com\/article\/3194147\/data-storage\/faq-3d-xpoint-memory-nand-flash-killer-or-dram-replacement.html.  Computer World. 2016. FAQ: 3D XPoint memory NAND flash killer or DRAM replacement? Available at www.computerworld.com\/article\/3194147\/data-storage\/faq-3d-xpoint-memory-nand-flash-killer-or-dram-replacement.html."},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859629"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488867"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080243"},{"key":"e_1_3_2_1_83_1","unstructured":"ZDNet. 2018. Wave Computing close to unveiling its first AI system. Available at www.zdnet.com\/article\/wave-computing-close-to-unveiling-its-first-ai-system.  ZDNet. 2018. Wave Computing close to unveiling its first AI system. Available at www.zdnet.com\/article\/wave-computing-close-to-unveiling-its-first-ai-system."},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477454"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.52"},{"volume-title":"Proceedings of the 23rd IEEE Symposium on High-Performance Computer Architecture (HPCA).","author":"Zhang Mingzhe","key":"e_1_3_2_1_86_1"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2015.7208275"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694370"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.47"},{"volume-title":"HNVM: Hybrid nvm enabled datacenter design and optimization. Technical Report MSR-TR-2017-8. Microsoft Research.","year":"2017","author":"Zhou Yanqi","key":"e_1_3_2_1_90_1"}],"event":{"name":"MEMSYS '18: The International Symposium on Memory Systems","acronym":"MEMSYS '18","location":"Alexandria Virginia USA"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240302.3240310","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3240302.3240310","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:08:01Z","timestamp":1750208881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240302.3240310"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":89,"alternative-id":["10.1145\/3240302.3240310","10.1145\/3240302"],"URL":"https:\/\/doi.org\/10.1145\/3240302.3240310","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]},"assertion":[{"value":"2018-10-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}