{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:31:17Z","timestamp":1750221077060,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":51,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,11,5]],"date-time":"2018-11-05T00:00:00Z","timestamp":1541376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,11,5]]},"DOI":"10.1145\/3240765.3240784","type":"proceedings-article","created":{"date-parts":[[2018,11,6]],"date-time":"2018-11-06T13:36:57Z","timestamp":1541511417000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Best of both worlds"],"prefix":"10.1145","author":[{"given":"Satwik","family":"Patnaik","sequence":"first","affiliation":[{"name":"New York University and New York University Abu Dhabi, United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammed","family":"Ashraf","sequence":"additional","affiliation":[{"name":"New York University and New York University Abu Dhabi, United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[{"name":"New York University and New York University Abu Dhabi, United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johann","family":"Knechtel","sequence":"additional","affiliation":[{"name":"New York University and New York University Abu Dhabi, United Arab Emirates"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,11,5]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Spectre attacks: Exploiting speculative execution,\" in Proc. S&P","author":"Kocher P.","year":"2019","unstructured":"P. Kocher et al., \"Spectre attacks: Exploiting speculative execution,\" in Proc. S&P, 2019."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2731342"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/3086723"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"e_1_3_2_1_5_1","article-title":"On the approximation resiliency of logic locking and IC camouflaging schemes","author":"Shamsi K.","year":"2018","unstructured":"K. Shamsi et al., \"On the approximation resiliency of logic locking and IC camouflaging schemes,\" Trans. IFS, 2018.","journal-title":"Trans. IFS"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516656"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903000"},{"key":"e_1_3_2_1_8_1","first-page":"443","volume-title":"ISVLSI","author":"Collantes M. I. M.","year":"2016","unstructured":"M. I. M. Collantes, M. E. Massad, and S. Garg, \"Threshold-dependent camouflaged cells to secure circuits against reverse engineering attacks,\" in Proc. ISVLSI, 2016, pp. 443--448."},{"key":"e_1_3_2_1_9_1","first-page":"1","volume-title":"ETS","author":"Nirmala I. R.","year":"2016","unstructured":"I. R. Nirmala et al., \"A novel threshold voltage defined switch for circuit camouflaging,\" in Proc. ETS, 2016, pp. 1--2."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310217"},{"key":"e_1_3_2_1_11_1","first-page":"109","article-title":"Chip-level anti-reverse engineering using transformable interconnects","author":"Chen S.","year":"2015","unstructured":"S. Chen et al., \"Chip-level anti-reverse engineering using transformable interconnects,\" in Proc. DFT, 2015, pp. 109--114.","journal-title":"Proc. DFT"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199706"},{"key":"e_1_3_2_1_13_1","first-page":"97","article-title":"Advancing hardware security using polymorphic and stochastic spin-hall effect devices","author":"Patnaik S.","year":"2018","unstructured":"S. Patnaik et al., \"Advancing hardware security using polymorphic and stochastic spin-hall effect devices,\" in Proc. DATE, 2018, pp. 97--102.","journal-title":"Proc. DATE"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485591"},{"key":"e_1_3_2_1_15_1","first-page":"605","volume-title":"ASPDAC","author":"Wang Y.","year":"2017","unstructured":"Y. Wang et al., \"Routing perturbation for enhanced security in split manufacturing,\" in Proc. ASPDAC, 2017, pp. 605--610."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/3201607.3201660"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196100"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2787754"},{"issue":"12","key":"e_1_3_2_1_19_1","article-title":"Are proximity attacks a threat to the security of split manufacturing of integrated circuits?","volume":"25","author":"Maga\u00f1a J.","year":"2017","unstructured":"J. Maga\u00f1a et al., \"Are proximity attacks a threat to the security of split manufacturing of integrated circuits?\" Trans. VLSI, vol. 25, no. 12, 2017.","journal-title":"Trans. VLSI"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199744"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2872335"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/2961880"},{"issue":"6","key":"e_1_3_2_1_23_1","first-page":"912","article-title":"Parasitic extraction for heterogeneous face-to-face bonded 3-D ICs","volume":"7","author":"Peng Y.","year":"2017","unstructured":"Y. Peng et al., \"Parasitic extraction for heterogeneous face-to-face bonded 3-D ICs,\" Trans. CPMT, vol. 7, no. 6, pp. 912--924, 2017.","journal-title":"Trans. CPMT"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593167"},{"key":"e_1_3_2_1_25_1","first-page":"188","volume-title":"ISSCC","author":"Kim D.H.","year":"2012","unstructured":"D.H. Kim et al., \"3D-MAPS: 3D massively parallel processor with stacked memory,\" in Proc. ISSCC, 2012, pp. 188--190."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","unstructured":"R. Radojcic More-than-Moore 2.5D and 3D SiP Integration. Springer 2017.","DOI":"10.5555\/3092616"},{"key":"e_1_3_2_1_27_1","first-page":"45","article-title":"Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration","volume":"10","author":"Knechtel J.","year":"2017","unstructured":"J. Knechtel et al., \"Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration,\" Trans. SLDM, vol. 10, pp. 45--62, 2017.","journal-title":"Trans. SLDM"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967013"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3177540.3178244"},{"key":"e_1_3_2_1_30_1","first-page":"331","volume-title":"IITC","author":"Peng Y.","year":"2015","unstructured":"Y. Peng et al., \"Thermal impact study of block folding and face-to-face bonding in 3D IC,\" in Proc. IITC, 2015, pp. 331--334."},{"volume-title":"Tech. Rep.","year":"2008","key":"e_1_3_2_1_31_1","unstructured":"Tezzaron Semiconductor, \"3D-ICs and integrated circuit security,\" Tezzaron Semiconductor, Tech. Rep., 2008. {Online}. Available: http:\/\/tezzaron.com\/media\/3D-ICs_and_Integrated_Circuit_Security.pdf"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060500"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903512"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.5555\/2534766.2534809"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2017.121"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2227257"},{"volume-title":"Unleashing VLSI to the Masses","key":"e_1_3_2_1_37_1","unstructured":"(2017) FreePDK: Unleashing VLSI to the Masses. Oklahoma State University. {Online}. Available: https:\/\/vlsiarch.ecen.okstate.edu\/flows\/"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967071"},{"issue":"7","key":"e_1_3_2_1_40_1","article-title":"Design methodologies for low-power 3-D ICs with advanced tier partitioning","volume":"25","author":"Jung M.","year":"2017","unstructured":"M. Jung et al., \"Design methodologies for low-power 3-D ICs with advanced tier partitioning,\" Trans. VLSI, vol. 25, no. 7, 2017.","journal-title":"Trans. VLSI"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2602554"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2601067"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1226325"},{"key":"e_1_3_2_1_44_1","unstructured":"(2011) NanGate FreePDK45 Open Cell Library. Nangate Inc. {Online}. Available: http:\/\/www.nangate.com\/?page_id=2325"},{"key":"e_1_3_2_1_45_1","unstructured":"(2018) DfX Lab NYUAD. {Online}. Available: http:\/\/sites.nyuad.nyu.edu\/dfx\/research-topics\/design-for-trust-split-manufacturing\/"},{"key":"e_1_3_2_1_46_1","first-page":"137","volume-title":"HOST","author":"Subramanyan P.","year":"2015","unstructured":"P. Subramanyan, S. Ray, and S. Malik, \"Evaluating the security of logic encryption algorithms,\" in Proc. HOST, 2015, pp. 137--143."},{"key":"e_1_3_2_1_47_1","volume-title":"A novel interconnect camouflaging technique using transistor threshold voltage,\" arXiv","author":"Jang J.","year":"2017","unstructured":"J. Jang and S. Ghosh, \"A novel interconnect camouflaging technique using transistor threshold voltage,\" arXiv, vol. abs\/1705.02707, 2017."},{"key":"e_1_3_2_1_48_1","first-page":"1","volume-title":"AHOST","author":"Dofe J.","year":"2016","unstructured":"J. Dofe et al., \"Transistor-level camouflaged logic locking method for monolithic 3D IC security,\" in Proc. AHOST, 2016, pp. 1--6."},{"issue":"6","key":"e_1_3_2_1_49_1","first-page":"799","article-title":"Hardware-efficient logic camouflaging for monolithic 3D ICs","volume":"65","author":"Yan C.","year":"2018","unstructured":"C. Yan et al., \"Hardware-efficient logic camouflaging for monolithic 3D ICs,\" Trans. CS, vol. 65, no. 6, pp. 799--803, 2018.","journal-title":"Trans. CS"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2015.23218"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2652220"}],"event":{"name":"ICCAD '18: IEEE\/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN","sponsor":["IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"],"location":"San Diego California","acronym":"ICCAD '18"},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240765.3240784","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3240765.3240784","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:57:33Z","timestamp":1750208253000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240765.3240784"}},"subtitle":["integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs"],"short-title":[],"issued":{"date-parts":[[2018,11,5]]},"references-count":51,"alternative-id":["10.1145\/3240765.3240784","10.1145\/3240765"],"URL":"https:\/\/doi.org\/10.1145\/3240765.3240784","relation":{},"subject":[],"published":{"date-parts":[[2018,11,5]]},"assertion":[{"value":"2018-11-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}