{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:31Z","timestamp":1780674751297,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,11,5]],"date-time":"2018-11-05T00:00:00Z","timestamp":1541376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,11,5]]},"DOI":"10.1145\/3240765.3240852","type":"proceedings-article","created":{"date-parts":[[2018,11,6]],"date-time":"2018-11-06T13:36:57Z","timestamp":1541511417000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Steep coverage-ascent directed test generation for shared-memory verification of multicore chips"],"prefix":"10.1145","author":[{"given":"Gabriel A. G.","family":"Andrade","sequence":"first","affiliation":[{"name":"Federal University of Santa Catarina, Florian\u00f3polis, Brazil"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marleson","family":"Graf","sequence":"additional","affiliation":[{"name":"Federal University of Santa Catarina, Florian\u00f3polis, Brazil"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"N\u00edcolas","family":"Pfeifer","sequence":"additional","affiliation":[{"name":"Federal University of Santa Catarina, Florian\u00f3polis, Brazil"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luiz C. V.","family":"dos Santos","sequence":"additional","affiliation":[{"name":"Federal University of Santa Catarina, Florian\u00f3polis, Brazil"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,11,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277900"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2013.373"},{"key":"e_1_3_2_1_4_1","unstructured":"Marco Elver. 2016. McVerSi Framework. https:\/\/github.com\/melver\/mc2lib. (2016)."},{"key":"e_1_3_2_1_5_1","volume-title":"IEEE Int. Symp. on High Performance Computer Architecture (HPCA). 618--630","author":"Elver M.","unstructured":"M. Elver and V. Nagarajan. 2016. McVerSi: A test generation framework for fast memory consistency verification in simulation. In IEEE Int. Symp. on High Performance Computer Architecture (HPCA). 618--630."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775907"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485444"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598123"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2209249.2209269"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","unstructured":"X. Qin and P. Mishra. 2012. Automated generation of directed tests for transition coverage in cache coherence protocols. In Design Automation and Test in Europe (DATE). 3--8.","DOI":"10.5555\/2492708.2492713"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771799"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","unstructured":"Ilya Wagner and Valeria Bertacco. 2008. MCjammer: Adaptive Verification for Multi-core Designs. In Design Automation and Test in Europe (DATE). 670--675. 10.1145\/1403375.1403539","DOI":"10.1145\/1403375.1403539"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.48"}],"event":{"name":"ICCAD '18: IEEE\/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN","location":"San Diego California","acronym":"ICCAD '18","sponsor":["IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240765.3240852","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3240765.3240852","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:57:33Z","timestamp":1750208253000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3240765.3240852"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11,5]]},"references-count":13,"alternative-id":["10.1145\/3240765.3240852","10.1145\/3240765"],"URL":"https:\/\/doi.org\/10.1145\/3240765.3240852","relation":{},"subject":[],"published":{"date-parts":[[2018,11,5]]},"assertion":[{"value":"2018-11-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}