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To debug hardware circuits, trace-based instrumentation is inserted into the design that enables capturing data during the circuit execution into on-chip memories for later offline analysis. Since on-chip memories are limited, a trigger circuitry is used to only record data related to specific events during the execution. However, during debugging, a circuit recompilation is required on modifying these instruments. This can be very slow, reducing debug productivity. In this article, we propose a non-intrusive and rapid triggering solution with a tailored overlay fabric and mapping algorithm that seeks to enable fast debug iterations without performing a recompilation. This overlay is specialized for small combinational and sequential circuits with a single output; such circuits are typical of common trigger functions. We present an adaptive strategy to construct the overlay fabric using spare FPGA resources at compile time. At debug time, our proposed trigger mapping algorithms adapt to this specialized overlay to rapidly implement combinational and sequential trigger circuits. Our results show that the overlay fabric can be reconfigured to map different triggering scenarios in less than 40s instead of recompiling the circuit during debug iterations, increasing debug productivity.<\/jats:p>","DOI":"10.1145\/3241045","type":"journal-article","created":{"date-parts":[[2018,12,6]],"date-time":"2018-12-06T13:34:16Z","timestamp":1544103256000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug"],"prefix":"10.1145","volume":"23","author":[{"given":"Fatemeh","family":"Eslami","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,12,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_2_1_2_1","unstructured":"Amazon. 2016. Amazon EC2 F1 Instances: Run Customizable FPGAs in the AWS Cloud. Retrieved from https:\/\/aws.amazon.com\/ec2\/instance-types\/f1\/.  Amazon. 2016. Amazon EC2 F1 Instances: Run Customizable FPGAs in the AWS Cloud. Retrieved from https:\/\/aws.amazon.com\/ec2\/instance-types\/f1\/."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437613"},{"key":"e_1_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Vaughn Betz Jonathan Rose and Alexander Marquardt (Eds.). 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic.   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