{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:17Z","timestamp":1750221257758,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,6,20]],"date-time":"2018-06-20T00:00:00Z","timestamp":1529452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,6,20]]},"DOI":"10.1145\/3241793.3241796","type":"proceedings-article","created":{"date-parts":[[2018,10,2]],"date-time":"2018-10-02T12:09:29Z","timestamp":1538482169000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Wibheda+"],"prefix":"10.1145","author":[{"given":"Deshya","family":"Wijesundera","sequence":"first","affiliation":[{"name":"Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alok","family":"Prakash","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thilina","family":"Perera","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kalindu","family":"Herath","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thambipillai","family":"Srikanthan","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2018,6,20]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2018. LLVM Compiler Infrastructure. http:\/\/llvm.org\/  2018. LLVM Compiler Infrastructure. http:\/\/llvm.org\/"},{"key":"e_1_3_2_1_2_1","unstructured":"Peter Arato et al. 2003. Hardware-software partitioning in embedded system design. In ISISP.  Peter Arato et al. 2003. Hardware-software partitioning in embedded system design. In ISISP."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996765"},{"volume-title":"Hardware-Software Partitioning in Embedded Systems","author":"Tom Brooks","key":"e_1_3_2_1_4_1","unstructured":"Tom Brooks . 2015. Hardware-Software Partitioning in Embedded Systems , Barr Group . http:\/\/bit.ly\/2fdqtbL Tom Brooks. 2015. Hardware-Software Partitioning in Embedded Systems, Barr Group. http:\/\/bit.ly\/2fdqtbL"},{"key":"e_1_3_2_1_5_1","volume-title":"Burg et al","author":"Jennifer J.","year":"1999","unstructured":"Jennifer J. Burg et al . 1999 . Experiments with the \"Oregon Trail Knapsack Problem\". Inform. Process. Lett . (1999). Jennifer J. Burg et al. 1999. Experiments with the \"Oregon Trail Knapsack Problem\". Inform. Process. Lett. (1999)."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Deming Chen et al. 2016. Platform choices and design demands for IoT platforms: cost power and performance tradeoffs. Cyber Physical Systems: Theory & Appl. (2016).  Deming Chen et al. 2016. Platform choices and design demands for IoT platforms: cost power and performance tradeoffs. Cyber Physical Systems: Theory & Appl. (2016).","DOI":"10.1049\/iet-cps.2016.0020"},{"key":"e_1_3_2_1_8_1","unstructured":"Helmut Demel. 2016. FPGAs solve challenges at the core of IoT implementation EDN. http:\/\/ubm.io\/2w1rE8S  Helmut Demel. 2016. FPGAs solve challenges at the core of IoT implementation EDN. http:\/\/ubm.io\/2w1rE8S"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Kratika Garg et al. 2015. KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs. In SOCC.  Kratika Garg et al. 2015. KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs. In SOCC.","DOI":"10.1109\/SOCC.2015.7406912"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Yuko Hara et al. 2009. Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. J. Inform. Process. (2009).  Yuko Hara et al. 2009. Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. J. Inform. Process. (2009).","DOI":"10.1109\/ISCAS.2008.4541637"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.924041"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2013.6567547"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2769125"},{"key":"e_1_3_2_1_14_1","unstructured":"Lattice Semiconductor. 2017. iCE40 Ultra\/UltraLite\/ UltraPlus-Lattice Semiconductor. http:\/\/bit.ly\/2n9SEhR  Lattice Semiconductor. 2017. iCE40 Ultra\/UltraLite\/ UltraPlus-Lattice Semiconductor. http:\/\/bit.ly\/2n9SEhR"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Malik Umar Sharif et al. 2016. Hardware-software Codesign of RSA for Optimal Performance vs. Flexibility Trade-off. In FPL.  Malik Umar Sharif et al. 2016. Hardware-software Codesign of RSA for Optimal Performance vs. Flexibility Trade-off. In FPL.","DOI":"10.1109\/FPL.2016.7577368"},{"key":"e_1_3_2_1_16_1","unstructured":"Anton Shilov. 2017. Intel Announces Cyclone 10 FPGAs for IoT Devices. http:\/\/bit.ly\/2m30SUX  Anton Shilov. 2017. Intel Announces Cyclone 10 FPGAs for IoT Devices. http:\/\/bit.ly\/2m30SUX"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.906457"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Deshya Wijesundera et al. 2016. Rapid Design Space Exploration for Soft Core Processor Customization and Selection. In FPT.  Deshya Wijesundera et al. 2016. Rapid Design Space Exploration for Soft Core Processor Customization and Selection. In FPT.","DOI":"10.1109\/FPT.2016.7929529"},{"key":"e_1_3_2_1_19_1","unstructured":"Peter Wilson. 2016. Design Recipes for FPGAs. Newnes Chapter 2.  Peter Wilson. 2016. Design Recipes for FPGAs. Newnes Chapter 2."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062195"}],"event":{"name":"HEART 2018: The 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies","acronym":"HEART 2018","location":"Toronto ON Canada"},"container-title":["Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3241793.3241796","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3241793.3241796","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:08:10Z","timestamp":1750212490000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3241793.3241796"}},"subtitle":["Framework for Data Dependency-aware Multi-constrained Hardware-Software Partitioning in FPGA-based SoCs for IoT Applications"],"short-title":[],"issued":{"date-parts":[[2018,6,20]]},"references-count":20,"alternative-id":["10.1145\/3241793.3241796","10.1145\/3241793"],"URL":"https:\/\/doi.org\/10.1145\/3241793.3241796","relation":{},"subject":[],"published":{"date-parts":[[2018,6,20]]},"assertion":[{"value":"2018-06-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}