{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T03:08:14Z","timestamp":1782788894467,"version":"3.54.5"},"reference-count":57,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2018,9,30]],"date-time":"2018-09-30T00:00:00Z","timestamp":1538265600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2018,9,30]]},"abstract":"<jats:p>Recently, deep learning (DL) has become best-in-class for numerous applications but at a high computational cost that necessitates high-performance energy-efficient acceleration. The reconfigurability of FPGAs is appealing due to the rapid change in DL models but also causes lower performance and area-efficiency compared to ASICs. In this article, we implement three state-of-the-art computing architectures (CAs) for convolutional neural network (CNN) inference on FPGAs and ASICs. By comparing the FPGA and ASIC implementations, we highlight the area and performance costs of programmability to pinpoint the inefficiencies in current FPGA architectures. We perform our experiments using three variations of these CAs for AlexNet, VGG-16 and ResNet-50 to allow extensive comparisons. We find that the performance gap varies significantly from 2.8\u00d7 to 6.3\u00d7, while the area gap is consistent across CAs with an 8.7 average FPGA-to-ASIC area ratio. Among different blocks of the CAs, the convolution engine, constituting up to 60% of the total area, has a high area ratio ranging from 13 to 31. Motivated by our FPGA vs. ASIC comparisons, we suggest FPGA architectural changes such as increasing DSP block count, enhancing low-precision support in DSP blocks and rethinking the on-chip memories to reduce the programmability gap for DL applications.<\/jats:p>","DOI":"10.1145\/3242898","type":"journal-article","created":{"date-parts":[[2018,12,12]],"date-time":"2018-12-12T12:49:32Z","timestamp":1544618972000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":66,"title":["You Cannot Improve What You Do not Measure"],"prefix":"10.1145","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8044-1644","authenticated-orcid":false,"given":"Andrew","family":"Boutros","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Toronto, ON, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1044-4460","authenticated-orcid":false,"given":"Sadegh","family":"Yazdanshenas","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Toronto, Ontario, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Toronto, ON, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2018,12,12]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the OSDI. 265--283","author":"Abadi M.","year":"2016"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021738"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"e_1_2_1_4_1","first-page":"127","article-title":"Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks","volume":"52","author":"Chen Y.","year":"2017","journal-title":"Proceedings of the JSSC"},{"key":"e_1_2_1_5_1","unstructured":"S. Chetlur etal 2014. CuDNN: Efficient primitives for deep learning. arXiv:1410.0759.  S. Chetlur et al. 2014. CuDNN: Efficient primitives for deep learning. arXiv:1410.0759."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the HOT CHIPS","volume":"29","author":"Chung E."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-55750-2_6"},{"key":"e_1_2_1_8_1","unstructured":"Y. Fu etal 2016. Deep learning with INT8 optimization on Xilinx devices. In white paper of Xilinx.  Y. Fu et al. 2016. Deep learning with INT8 optimization on Xilinx devices. In white paper of Xilinx."},{"key":"e_1_2_1_9_1","unstructured":"L. Gatys etal 2015. A neural algorithm of artistic style. arXiv:1508.06576.  L. Gatys et al. 2015. A neural algorithm of artistic style. arXiv:1508.06576."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2013.6638947"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.25"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980098"},{"key":"e_1_2_1_13_1","unstructured":"P. Gysel etal 2016. Hardware-oriented approximation of convolutional neural networks. arXiv:1604.03168.  P. Gysel et al. 2016. Hardware-oriented approximation of convolutional neural networks. arXiv:1604.03168."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2015.123"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.3389\/neuro.09.031.2009"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the ICML. 448--456","author":"Ioffe S."},{"key":"e_1_2_1_18_1","volume-title":"Caffe: Convolutional architecture for fast feature embedding. arXiv:1408.5093.","author":"Jia Y.","year":"2014"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the NIPS. 1097--1105","author":"Krizhevsky A.","year":"2012"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689071"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the CVPR. 4013--4021","author":"Lavin A."},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the FPT. 61--68","author":"Liu Z.","year":"2016"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.64"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the FPL. 1--8.","author":"Ma Y.","year":"2016"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056824"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"e_1_2_1_28_1","volume-title":"WRPN: Wide reduced-precision networks. arXiv:1709.01134.","author":"Mishra A.","year":"2017"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929192"},{"key":"e_1_2_1_30_1","volume-title":"Microsoft Research Whitepaper","volume":"2","author":"Ovtcharov K.","year":"2015"},{"key":"e_1_2_1_31_1","volume-title":"Prost-Boucle et al","author":"A.","year":"2017"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2014.7082748"},{"key":"e_1_2_1_35_1","doi-asserted-by":"crossref","unstructured":"D. E. Rumelhart etal 1985. Learning Internal Representations by Error Propagation. Technical Report.  D. E. Rumelhart et al. 1985. Learning Internal Representations by Error Propagation. Technical Report.","DOI":"10.21236\/ADA164453"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195659"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAI.2016.7811085"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577315"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080221"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature24270"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"e_1_2_1_43_1","doi-asserted-by":"crossref","unstructured":"A. Suleiman etal 2017. Towards closing the energy Gap between HOG and CNN features for embedded vision. arXiv:1703.05853.  A. Suleiman et al. 2017. Towards closing the energy Gap between HOG and CNN features for embedded vision. arXiv:1703.05853.","DOI":"10.1109\/ISCAS.2017.8050341"},{"key":"e_1_2_1_44_1","volume-title":"Proceedings of the NIPS. 3104--3112","author":"Sutskever I.","year":"2014"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"e_1_2_1_46_1","volume-title":"Proceedings of the FPT. 4--11"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"e_1_2_1_48_1","volume-title":"Proceedings of the FCCM. 40--47","author":"Venieris S."},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2017.7952679"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.5555\/3130379.3130625"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898003"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062207"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021731"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934644"},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021727"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3242898","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3242898","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T01:39:24Z","timestamp":1750210764000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3242898"}},"subtitle":["FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference"],"short-title":[],"issued":{"date-parts":[[2018,9,30]]},"references-count":57,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,9,30]]}},"alternative-id":["10.1145\/3242898"],"URL":"https:\/\/doi.org\/10.1145\/3242898","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,9,30]]},"assertion":[{"value":"2017-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2018-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}