{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,21]],"date-time":"2026-03-21T19:23:22Z","timestamp":1774121002741,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":49,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,11,1]],"date-time":"2018-11-01T00:00:00Z","timestamp":1541030400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Research Foundation of Korea","award":["NRF-2015K1A3A1A14021288, 21A20151113068"],"award-info":[{"award-number":["NRF-2015K1A3A1A14021288, 21A20151113068"]}]},{"name":"Seoul National University","award":["Promising- Pioneering Researcher Program (2015)"],"award-info":[{"award-number":["Promising- Pioneering Researcher Program (2015)"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1145\/3243176.3243199","type":"proceedings-article","created":{"date-parts":[[2018,10,10]],"date-time":"2018-10-10T13:32:32Z","timestamp":1539178352000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Maximizing system utilization via parallelism management for co-located parallel applications"],"prefix":"10.1145","author":[{"given":"Younghyun","family":"Cho","sequence":"first","affiliation":[{"name":"Seoul National University, Seoul, South Korea"}]},{"given":"Camilo A. Celis","family":"Guzman","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, South Korea"}]},{"given":"Bernhard","family":"Egger","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, South Korea"}]}],"member":"320","published-online":{"date-parts":[[2018,11]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2018. GNU libgomp. http:\/\/gcc.gnu.org\/onlinedocs\/libgomp\/. (2018). {online; accessed July 2018}.  2018. GNU libgomp. http:\/\/gcc.gnu.org\/onlinedocs\/libgomp\/. (2018). {online; accessed July 2018}."},{"key":"e_1_3_2_1_2_1","unstructured":"AMD. 2012. BIOS and kernel developer's guide (BKDG) for AMD family 15h models 00h-0fh processors. (2012).  AMD. 2012. BIOS and kernel developer's guide (BKDG) for AMD family 15h models 00h-0fh processors. (2012)."},{"key":"e_1_3_2_1_3_1","unstructured":"AMD. 2014. Revision Guide for AMD Family 15h Models 00h-0Fh Processors. (2014).  AMD. 2014. Revision Guide for AMD Family 15h Models 00h-0Fh Processors. (2014)."},{"key":"e_1_3_2_1_4_1","unstructured":"AMD. 2018. AMD Opteron 6300 Series Processors. http:\/\/www.amd.com\/en-us\/products\/server\/opteron\/6000\/6300. (2018). {online; accessed July 2018}.  AMD. 2018. AMD Opteron 6300 Series Processors. http:\/\/www.amd.com\/en-us\/products\/server\/opteron\/6000\/6300. (2018). {online; accessed July 2018}."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629579"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_8_1","volume-title":"http:\/\/openmp.org. (2018). {online","author":"Architecture Review Board MP","year":"2018","unstructured":"Open MP Architecture Review Board . 2018. Open MP. http:\/\/openmp.org. (2018). {online ; accessed July 2018 }. OpenMP Architecture Review Board. 2018. OpenMP. http:\/\/openmp.org. (2018). {online; accessed July 2018}."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTER.2017.59"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2015.38"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967960"},{"key":"e_1_3_2_1_13_1","volume-title":"Job Scheduling Strategies for Parallel Processing. JSSPP","author":"Cho Younghyun","year":"2015","unstructured":"Younghyun Cho , Surim Oh , and Bernhard Egger . 2017. Adaptive Space-Shared Scheduling for Shared-Memory Parallel Programs . In Job Scheduling Strategies for Parallel Processing. JSSPP 2015 , JSSPP 2016. Lecture Notes in Computer Science, vol. 10353 . Springer International Publishing , Cham, 158--177. Younghyun Cho, Surim Oh, and Bernhard Egger. 2017. Adaptive Space-Shared Scheduling for Shared-Memory Parallel Programs. In Job Scheduling Strategies for Parallel Processing. JSSPP 2015, JSSPP 2016. Lecture Notes in Computer Science, vol. 10353. Springer International Publishing, Cham, 158--177."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540737"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451157"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2737924.2737999"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3064176.3064177"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944881"},{"key":"e_1_3_2_1_19_1","volume-title":"SnuMAP: an Open-source Trace Profiler for Manycore Systems. https:\/\/csap.snu.ac.kr\/software\/snumap\/. (2017). {online","author":"Celis Guzman Camilo A.","year":"2018","unstructured":"Camilo A. Celis Guzman , Younghyun Cho , and Bernhard Egger . 2017. SnuMAP: an Open-source Trace Profiler for Manycore Systems. https:\/\/csap.snu.ac.kr\/software\/snumap\/. (2017). {online ; accessed July 2018 }. Camilo A. Celis Guzman, Younghyun Cho, and Bernhard Egger. 2017. SnuMAP: an Open-source Trace Profiler for Manycore Systems. https:\/\/csap.snu.ac.kr\/software\/snumap\/. (2017). {online; accessed July 2018}."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592807"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835975"},{"key":"e_1_3_2_1_22_1","unstructured":"Intel. 2015. Intel 64 and IA-32 Architectures Software Developer's Manual. (2015).  Intel. 2015. Intel 64 and IA-32 Architectures Software Developer's Manual. (2015)."},{"key":"e_1_3_2_1_23_1","unstructured":"Intel. 2015. Intel Xeon Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual. (2015).  Intel. 2015. Intel Xeon Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual. (2015)."},{"key":"e_1_3_2_1_24_1","unstructured":"Intel. 2018. Intel Performance Counter Monitor - A better way to measure CPU utilization. http:\/\/www.intel.com\/software\/pcm. (2018). {online; accessed July 2018}.  Intel. 2018. Intel Performance Counter Monitor - A better way to measure CPU utilization. http:\/\/www.intel.com\/software\/pcm. (2018). {online; accessed July 2018}."},{"key":"e_1_3_2_1_25_1","unstructured":"Intel. 2018. Intel Xeon Processor E7-8870 v3. http:\/\/ark.intel.com\/products\/84682\/Intel-Xeon-Processor-E7-8870-v3-45M-Cache-2_10-GHz. (2018). {online; accessed July 2018}.  Intel. 2018. Intel Xeon Processor E7-8870 v3. http:\/\/ark.intel.com\/products\/84682\/Intel-Xeon-Processor-E7-8870-v3-45M-Cache-2_10-GHz. (2018). {online; accessed July 2018}."},{"key":"e_1_3_2_1_26_1","volume-title":"Computer Performance Evaluation Modelling Techniques and Tools","author":"Jonkers Henk","unstructured":"Henk Jonkers . 1994. Queueing models of parallel applications: the Glamis methodology . In Computer Performance Evaluation Modelling Techniques and Tools . Springer , 123--138. Henk Jonkers. 1994. Queueing models of parallel applications: the Glamis methodology. In Computer Performance Evaluation Modelling Techniques and Tools. Springer, 123--138."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400704"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815996"},{"key":"e_1_3_2_1_29_1","volume-title":"Proceedings of the First USENIX Conference on Hot Topics in Parallelism (HotPar'09)","author":"Liu Rose","year":"2009","unstructured":"Rose Liu , Kevin Klues , Sarah Bird , Steven Hofmeyr , Krste Asanovi\u0107 , and John Kubiatowicz . 2009 . Tessellation: Space-time Partitioning in a Manycore Client OS . In Proceedings of the First USENIX Conference on Hot Topics in Parallelism (HotPar'09) . USENIX Association, Berkeley, CA, USA, 10--10. http:\/\/dl.acm.org\/citation.cfm?id= 1855591.1855601 Rose Liu, Kevin Klues, Sarah Bird, Steven Hofmeyr, Krste Asanovi\u0107, and John Kubiatowicz. 2009. Tessellation: Space-time Partitioning in a Manycore Client OS. In Proceedings of the First USENIX Conference on Hot Topics in Parallelism (HotPar'09). USENIX Association, Berkeley, CA, USA, 10--10. http:\/\/dl.acm.org\/citation.cfm?id=1855591.1855601"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2901318.2901326"},{"key":"e_1_3_2_1_31_1","volume-title":"2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. 164--171","author":"Luo Kun","year":"2001","unstructured":"Kun Luo , Jayanth Gummaraju , and Manoj Franklin . 2001 . Balancing thoughput and fairness in SMT processors . In 2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. 164--171 . Kun Luo, Jayanth Gummaraju, and Manoj Franklin. 2001. Balancing thoughput and fairness in SMT processors. In 2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. 164--171."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2076022.1993481"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259046"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189220"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2010.5642789"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993502"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254082"},{"key":"e_1_3_2_1_39_1","volume-title":"Intel threading building blocks: outfitting C++ for multi-core processor parallelism","author":"Reinders James","unstructured":"James Reinders . 2007. Intel threading building blocks: outfitting C++ for multi-core processor parallelism . O'Reilly Media, Inc. James Reinders. 2007. Intel threading building blocks: outfitting C++ for multi-core processor parallelism. O'Reilly Media, Inc."},{"key":"e_1_3_2_1_40_1","volume-title":"Hypertransport Technology. Platform Conference","author":"Sartori Gabriele","year":"2001","unstructured":"Gabriele Sartori . 2001 . Hypertransport Technology. Platform Conference (2001). Gabriele Sartori. 2001. Hypertransport Technology. Platform Conference (2001)."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/2523721.2523732"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370833"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2011.6114174"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2594291.2594292"},{"key":"e_1_3_2_1_45_1","volume-title":"2015 USENIX Annual Technical Conference (USENIX ATC 15)","author":"Srikanthan Sharanyan","year":"2015","unstructured":"Sharanyan Srikanthan , Sandhya Dwarkadas , and Kai Shen . 2015 . Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems . In 2015 USENIX Annual Technical Conference (USENIX ATC 15) . USENIX Association, Santa Clara, CA, 529--540. https:\/\/www.usenix.org\/conference\/atc15\/technical-session\/presentation\/srikanthan Sharanyan Srikanthan, Sandhya Dwarkadas, and Kai Shen. 2015. Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems. In 2015 USENIX Annual Technical Conference (USENIX ATC 15). USENIX Association, Santa Clara, CA, 529--540. https:\/\/www.usenix.org\/conference\/atc15\/technical-session\/presentation\/srikanthan"},{"key":"e_1_3_2_1_46_1","volume-title":"Basic queueing theory","author":"Sztrik J\u00e1nos","year":"2011","unstructured":"J\u00e1nos Sztrik . 2011. Basic queueing theory . University of Debrecen : Faculty of Informatics ( 2011 ). J\u00e1nos Sztrik. 2011. Basic queueing theory. University of Debrecen: Faculty of Informatics (2011)."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.68"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2011.59"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807132"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"}],"event":{"name":"PACT '18: International conference on Parallel Architectures and Compilation Techniques","location":"Limassol Cyprus","acronym":"PACT '18","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IFIP WG 10.3 IFIP WG 10.3","IEEE CS"]},"container-title":["Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3243176.3243199","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3243176.3243199","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T00:57:39Z","timestamp":1750208259000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3243176.3243199"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11]]},"references-count":49,"alternative-id":["10.1145\/3243176.3243199","10.1145\/3243176"],"URL":"https:\/\/doi.org\/10.1145\/3243176.3243199","relation":{},"subject":[],"published":{"date-parts":[[2018,11]]},"assertion":[{"value":"2018-11-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}